Cost-effective multi-standard video transform core using time-sharing architecture

Yun Hua Tseng; Yuan Ho Chen; Chih Wen Lu

doi:10.1109/ISNE.2016.7543357

Cost-effective multi-standard video transform core using time-sharing architecture

Yun Hua Tseng
, Yuan Ho Chen
, Chih Wen Lu

Department of Electronic Engineering

National Tsing Hua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.

Original language	English
Title of host publication	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509024391
DOIs	https://doi.org/10.1109/ISNE.2016.7543357
State	Published - 12 08 2016
Event	5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan Duration: 04 05 2016 → 06 05 2016

Publication series

Name	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Conference

Conference	5th International Symposium on Next-Generation Electronics, ISNE 2016
Country/Territory	Taiwan
City	Hsinchu
Period	04/05/16 → 06/05/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

Two-dimensional inverse discrete cosine transform (2D-IDCT)
cost-efficitive
distributed arithmetic (DA)
multi-standard transform
time-sharing

Access to Document

10.1109/ISNE.2016.7543357

Cite this

Tseng, Y. H., Chen, Y. H., & Lu, C. W. (2016). Cost-effective multi-standard video transform core using time-sharing architecture. In 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 Article 7543357 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISNE.2016.7543357

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title = "Cost-effective multi-standard video transform core using time-sharing architecture",

abstract = "This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100\%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.",

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author = "Tseng, \{Yun Hua\} and Chen, \{Yuan Ho\} and Lu, \{Chih Wen\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 5th International Symposium on Next-Generation Electronics, ISNE 2016 ; Conference date: 04-05-2016 Through 06-05-2016",

year = "2016",

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day = "12",

doi = "10.1109/ISNE.2016.7543357",

language = "英语",

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}

Tseng, YH, Chen, YH & Lu, CW 2016, Cost-effective multi-standard video transform core using time-sharing architecture. in 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016., 7543357, 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016, Institute of Electrical and Electronics Engineers Inc., 5th International Symposium on Next-Generation Electronics, ISNE 2016, Hsinchu, Taiwan, 04/05/16. https://doi.org/10.1109/ISNE.2016.7543357

Cost-effective multi-standard video transform core using time-sharing architecture. / Tseng, Yun Hua; Chen, Yuan Ho; Lu, Chih Wen.
2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7543357 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.

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Cost-effective multi-standard video transform core using time-sharing architecture

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Keywords

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