Cost-efficient design and fixed-point analysis of IFFT/FFT processor chip for OFDM systems

Ting Yuan Chen*, Yi Hsien Lin, Chih Feng Wu, Chorng Kuang Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

In this paper, a cost-efficient raultiplierless IFFT/FFT processor with its fixed-point error analysis is presented. The IFFT/FFT processor employs the radix-2/4/8 algorithm, and a proposed classification of twiddle factors (TW) and hardware sharing are used to minimize the nonzero bits of the shift-and-adds operations. After the appropriate wordlengths (WL) of the TWs and the IFFT/FFT processor input are chosen by the proposed fixed-point quantization noise analysis, a hardwarelike fixed-point simulation model of the IFFT/FFT processor is used to develop the Verilog RTL code. The proposed IFFT/FFT processor can achieve packet error rate(PER) less than 0.1 for the test vehicle IEEE 802.11a single-input-single-output (SISO)-OFDM system and slight symbol error rate(SER) loss for the IEEE 802.11n multi-input-multi-output (MIMO)-OFDM system. The core area of the one processor chip is 0.57umx0.565um with 0.18um CMOS process. Besides, the power consumption is 7.74 mW with 1.8 V supply voltage and 40 Mhz system clock.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages91-94
Number of pages4
DOIs
StatePublished - 2011
Externally publishedYes
Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
Duration: 25 04 201128 04 2011

Publication series

NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country/TerritoryTaiwan
CityHsinchu
Period25/04/1128/04/11

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