TY - GEN
T1 - Cost efficient FEQ implementation for IEEE 802.16a OFDM transceiver
AU - Lin, Chih Hsien
AU - Lin, Yi Hsien
AU - Wu, Chih Feng
AU - Shiue, Muh Tian
AU - Wang, Chorng Kuang
PY - 2009
Y1 - 2009
N2 - Based on SR transformation, a cost efficient FEQ is proposed for OFDM transceiver of IEEE 802.16a WMAN without SNR loss over the multipath fading channel. The cost efficient FEQ is composed of three parts: channel estimation, filtering and updating processes. Significantly, the computing complexity of multiplication for the cost efficient approach can totally yield 19% reduction compared with the conventional approach. In view of the memory arrangement in VLSI design, the area and power can be decreased by 70% and 50% respectively for the channel estimation. In the updating, 18% reduction is obtained for both area and power. According to the uncoded SER simulation, the proposed approach is identical with the conventional approach. Finally, the cost efficient FEQ is demonstrated by FPGA board.
AB - Based on SR transformation, a cost efficient FEQ is proposed for OFDM transceiver of IEEE 802.16a WMAN without SNR loss over the multipath fading channel. The cost efficient FEQ is composed of three parts: channel estimation, filtering and updating processes. Significantly, the computing complexity of multiplication for the cost efficient approach can totally yield 19% reduction compared with the conventional approach. In view of the memory arrangement in VLSI design, the area and power can be decreased by 70% and 50% respectively for the channel estimation. In the updating, 18% reduction is obtained for both area and power. According to the uncoded SER simulation, the proposed approach is identical with the conventional approach. Finally, the cost efficient FEQ is demonstrated by FPGA board.
UR - http://www.scopus.com/inward/record.url?scp=77950681410&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2009.5158118
DO - 10.1109/VDAT.2009.5158118
M3 - 会议稿件
AN - SCOPUS:77950681410
SN - 9781424427826
T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
SP - 154
EP - 157
BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Y2 - 28 April 2009 through 30 April 2009
ER -