Degradation mechanisms in gate-all-around silicon Nanowire field effect transistor under electrostatic discharge stress a modeling approach

Cher Ming Tan*, Xiangchen Chen

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

2 Scopus citations

Abstract

The failure and degradation mechanisms of gate-all-around silicon nanowire FET subjected to electrostatic discharge (ESD) are investigated through device modeling. Transmission line pulse stress test is simulated and device degradation physics is modeled. The device degradation level, interface state concentration and hard breakdown are shown and analyzed. From the model, we found that ESD stress can induce severe performance degradation or even hard breakdown of gate-all-around nanowire device, and the interface traps due to hot carrier injection is responsible for the device degradation.

Original languageEnglish
Article number11
JournalNano Convergence
Volume1
Issue number1
DOIs
StatePublished - 12 2014
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2014, Tan and Chen.

Keywords

  • ESD
  • Hot carrier injection
  • Oxide breakdown
  • Sentaurus simulation
  • Silicon melting

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