Design and Implementation of a Very-Large-Scale Integration–Based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems

This paper explores the architectural design and implementation of an Ising-model-based chip for solving combinatorial optimization problems. The proposed chip, which is fabricated through TSMC’s 90-nm complementary metal–oxide–semiconductor process, operates at 100 MHz, has a core area of 1.46×1.47 mm2, and exhibits a power consumption of 13.6 mW. The leveraging of the fully connected topology of this chip eliminates the need for spin transformations, which results in high efficiency per spin. Comparative analysis reveals that the proposed chip outperforms similar designs in terms of normalized spin area. This study contributes substantially to the advancement of Ising chips by developing an Ising chip with a suitable balance of power, area, and frequency.