TY - GEN
T1 - Design and implementation of reconfigurable IDCT architecture for multi-standard video decoders
AU - Lai, Yu Fan
AU - Lai, Yeong Kang
PY - 2010
Y1 - 2010
N2 - In this paper, we propose a reconfigurable IDCT architecture for multi-standard video decoders. It can support different video standards such as MPEG-1/2/4, VC-1 and H.264 AVC. Moreover, the particular part of this architecture does not use any multiplier and ROM circuit; it only needs adders and shifters. In digital circuit, the area of adders and shifters are superior to multipliers and ROM, The reconfigurable IDCT architecture only needs 13 adders in the adder kernel. Finally, we realize this architecture by using 0.18um technology to accomplish the chip design. The experimental result shows the total gate counts only 12.4 K. Moreover, the power consumption is 4.85mW@100MHz. Therefore, the architecture is regular and suitable for multi-standard video decoders.
AB - In this paper, we propose a reconfigurable IDCT architecture for multi-standard video decoders. It can support different video standards such as MPEG-1/2/4, VC-1 and H.264 AVC. Moreover, the particular part of this architecture does not use any multiplier and ROM circuit; it only needs adders and shifters. In digital circuit, the area of adders and shifters are superior to multipliers and ROM, The reconfigurable IDCT architecture only needs 13 adders in the adder kernel. Finally, we realize this architecture by using 0.18um technology to accomplish the chip design. The experimental result shows the total gate counts only 12.4 K. Moreover, the power consumption is 4.85mW@100MHz. Therefore, the architecture is regular and suitable for multi-standard video decoders.
KW - IDCT
KW - Multi-standard
KW - Reconfigurable architecture
UR - http://www.scopus.com/inward/record.url?scp=79851471033&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2010.5682962
DO - 10.1109/SOCDC.2010.5682962
M3 - 会议稿件
AN - SCOPUS:79851471033
SN - 9781424486335
T3 - 2010 International SoC Design Conference, ISOCC 2010
SP - 107
EP - 110
BT - 2010 International SoC Design Conference, ISOCC 2010
T2 - 2010 International SoC Design Conference, ISOCC 2010
Y2 - 22 November 2010 through 23 November 2010
ER -