Design and implementation of reconfigurable IDCT architecture for multi-standard video decoders

Yu Fan Lai*, Yeong Kang Lai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, we propose a reconfigurable IDCT architecture for multi-standard video decoders. It can support different video standards such as MPEG-1/2/4, VC-1 and H.264 AVC. Moreover, the particular part of this architecture does not use any multiplier and ROM circuit; it only needs adders and shifters. In digital circuit, the area of adders and shifters are superior to multipliers and ROM, The reconfigurable IDCT architecture only needs 13 adders in the adder kernel. Finally, we realize this architecture by using 0.18um technology to accomplish the chip design. The experimental result shows the total gate counts only 12.4 K. Moreover, the power consumption is 4.85mW@100MHz. Therefore, the architecture is regular and suitable for multi-standard video decoders.

Original languageEnglish
Title of host publication2010 International SoC Design Conference, ISOCC 2010
Pages107-110
Number of pages4
DOIs
StatePublished - 2010
Externally publishedYes
Event2010 International SoC Design Conference, ISOCC 2010 - Incheon, Korea, Republic of
Duration: 22 11 201023 11 2010

Publication series

Name2010 International SoC Design Conference, ISOCC 2010

Conference

Conference2010 International SoC Design Conference, ISOCC 2010
Country/TerritoryKorea, Republic of
CityIncheon
Period22/11/1023/11/10

Keywords

  • IDCT
  • Multi-standard
  • Reconfigurable architecture

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