TY - GEN
T1 - Design-for-testability techniques for arithmetic circuits
AU - Ye, Bo Yuan
AU - Yeh, Po Yu
AU - Kuo, Sy Yen
AU - Chen, Ing Yi
PY - 2009
Y1 - 2009
N2 - In this paper, a novel test technique is proposed to achieve C-testable DFT designs for arithmetic circuits. Base on famous iterative-logic-array (ILA) test scheme, basic bijective cells (one-to-one mapped I/O function) for adder, subtractor, adder-subtractor and multiplier are proposed. In particular, these basic cells are always bijective for any word-length n. Thus the bijective cells can be easily connected together for various arithmetic circuits such as accumulator, multiplier and FIR (Finite Impulse Response) filter, and these arithmetic circuits can be regarded as C-testable ILAs. The proposed solutions can be reused or cascaded with similar structure circuits. Besides, all the proposed arithmetic DFT designs can be cascaded and tested together for saving lots of test pins and BIST (Build-In Self Test) area.
AB - In this paper, a novel test technique is proposed to achieve C-testable DFT designs for arithmetic circuits. Base on famous iterative-logic-array (ILA) test scheme, basic bijective cells (one-to-one mapped I/O function) for adder, subtractor, adder-subtractor and multiplier are proposed. In particular, these basic cells are always bijective for any word-length n. Thus the bijective cells can be easily connected together for various arithmetic circuits such as accumulator, multiplier and FIR (Finite Impulse Response) filter, and these arithmetic circuits can be regarded as C-testable ILAs. The proposed solutions can be reused or cascaded with similar structure circuits. Besides, all the proposed arithmetic DFT designs can be cascaded and tested together for saving lots of test pins and BIST (Build-In Self Test) area.
KW - C-testable
KW - Design for testability
KW - Iterative logic array
KW - Logic testing
UR - http://www.scopus.com/inward/record.url?scp=70149117726&partnerID=8YFLogxK
U2 - 10.1109/CAS-ICTD.2009.4960806
DO - 10.1109/CAS-ICTD.2009.4960806
M3 - 会议稿件
AN - SCOPUS:70149117726
SN - 9781424425877
T3 - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
BT - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
T2 - 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
Y2 - 28 April 2009 through 29 April 2009
ER -