Design of a CMOS quadrature VCO with current reuse method

This work presents the design of a CMOS quadrature voltage-controlled oscillator (QVCO) constructed in a totem-pole configuration in order to reuse the bias current and lower the power consumption. A new feature of using four RC delay lines connected at the output ports of an oscillator is adopted in order to obtain the desired quadrature phase shift of the oscillation signals. An experimental chip is designed and fabricated using 0.18-μm CMOS technology to verify the effectiveness of the design concept. The measurement result shows that the center oscillation frequency of the prototype is 6.3 GHz, associated with a 100-MHz tuning range and - 108.7-dBc/Hz phase noise at 1-MHz offset.