@inproceedings{9caa27e693ab4d01a3728fae93e70309,
title = "Design of a digital VLSI neuroprocessor for signal and image processing",
abstract = "An efficient processing element for data/image processing has been designed. Detailed communication networks, instruction sets and circuit blocks are created for ring-connected and mesh-connected systolic arrays for the retrieving and learning phases of the neural network operations. 800 processing elements can be implemented in 3.75 cm × 3.75 cm chip by using the 0.5 μm CMOS technology from TRW, Inc. This digital neuroprocessor can also be extended to support fuzzy logic inference.",
author = "Chang, \{Chia Fen\} and Sheu, \{Bing J.\}",
year = "1991",
language = "英语",
isbn = "0780301188",
series = "Neural Networks for Signal Processing",
publisher = "Publ by IEEE",
pages = "606--615",
booktitle = "Neural Networks for Signal Processing",
note = "Proceedings of the 1991 Workshop on Neural Networks for Signal Processing - NNSP-91 ; Conference date: 30-09-1991 Through 02-10-1991",
}