Design of a transparent pipeline-based multiplier

Ren Der Chen; Xiang Chih Kuo

doi:10.1007/978-3-319-17314-6_62

Design of a transparent pipeline-based multiplier

Ren Der Chen
, Xiang Chih Kuo^*

^*Corresponding author for this work

National Changhua University of Education

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.

Original language	English
Title of host publication	Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
Editors	Jengnan Juang
Publisher	Springer Verlag
Pages	485-491
Number of pages	7
ISBN (Print)	9783319173139
DOIs	https://doi.org/10.1007/978-3-319-17314-6_62
State	Published - 2016
Externally published	Yes
Event	3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 - Kaohsiung, Taiwan Duration: 19 12 2014 → 21 12 2014

Publication series

Name	Lecture Notes in Electrical Engineering
Volume	345
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Conference

Conference	3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
Country/Territory	Taiwan
City	Kaohsiung
Period	19/12/14 → 21/12/14

Bibliographical note

Publisher Copyright:
© Springer International Publishing Switzerland 2016.

Keywords

Multiplier
Sparse matrix
Transparent pipeline

Access to Document

10.1007/978-3-319-17314-6_62

Cite this

@inproceedings{ab440cdd0e65479ebdbecd43c85da25e,

title = "Design of a transparent pipeline-based multiplier",

abstract = "This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.",

keywords = "Multiplier, Sparse matrix, Transparent pipeline",

author = "Chen, \{Ren Der\} and Kuo, \{Xiang Chih\}",

note = "Publisher Copyright: {\textcopyright} Springer International Publishing Switzerland 2016.; 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 ; Conference date: 19-12-2014 Through 21-12-2014",

year = "2016",

doi = "10.1007/978-3-319-17314-6\_62",

language = "英语",

isbn = "9783319173139",

series = "Lecture Notes in Electrical Engineering",

publisher = "Springer Verlag",

pages = "485--491",

editor = "Jengnan Juang",

booktitle = "Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014",

address = "德国",

}

Chen, RD & Kuo, XC 2016, Design of a transparent pipeline-based multiplier. in J Juang (ed.), Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. Lecture Notes in Electrical Engineering, vol. 345, Springer Verlag, pp. 485-491, 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014, Kaohsiung, Taiwan, 19/12/14. https://doi.org/10.1007/978-3-319-17314-6_62

Design of a transparent pipeline-based multiplier. / Chen, Ren Der; Kuo, Xiang Chih.
Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014. ed. / Jengnan Juang. Springer Verlag, 2016. p. 485-491 (Lecture Notes in Electrical Engineering; Vol. 345).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of a transparent pipeline-based multiplier

AU - Chen, Ren Der

AU - Kuo, Xiang Chih

N1 - Publisher Copyright: © Springer International Publishing Switzerland 2016.

PY - 2016

Y1 - 2016

N2 - This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.

AB - This chapter implements an 8 x 8 multiplier based on the transparent pipeline architecture. A transparent pipeline can lower the power consumption by reducing the number of clock pulses required for data latch controlling. The efficiency of power saving is evaluated here by applying the multiplier to the multiplication of two sparse matrices. It can be seen from the experimental results that, when compared with the traditional synchronous multiplier using flip-flops as storage elements, the improvement in power consumption is obvious only when the sparsity of the matrix reaches a certain amount.

KW - Multiplier

KW - Sparse matrix

KW - Transparent pipeline

UR - https://www.scopus.com/pages/publications/84951918795

U2 - 10.1007/978-3-319-17314-6_62

DO - 10.1007/978-3-319-17314-6_62

M3 - 会议稿件

AN - SCOPUS:84951918795

SN - 9783319173139

T3 - Lecture Notes in Electrical Engineering

SP - 485

EP - 491

BT - Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014

A2 - Juang, Jengnan

PB - Springer Verlag

T2 - 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014

Y2 - 19 December 2014 through 21 December 2014

ER -

Design of a transparent pipeline-based multiplier

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this