Design of a transparent pipeline based on synchronous elastic circuits

This chapter presents a transparent pipeline architecture based on the synchronous elastic circuits. Compared with a traditional synchronous pipeline, a transparent pipeline can reduce dynamic clock power dissipation by reducing the amount of clock pulses required for data latching. Moreover, with the help of the synchronous elastic properties, our design can also provide tolerance to variations in computation and communication delays. The proposed architecture has been implemented by the Verilog HDL and synthesized with Altera Quartus II. The experimental results performed on a five-stage pipeline have also shown the power efficiency of our architecture.