Design of an asynchronous pipelined processor

Meng Chou Chang*, Da Sen Shiau

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Asynchronous circuits have the potential advantages of low power consumption, high operating speed, low electromagnetic emission, no clock skew problem, and robustness towards variations in temperature, supply voltage and fabrication process parameters. This paper introduces the design of an asynchronous pipelined processor, called AsynRISC, which is implemented by using the asynchronous hardware description language Balsa. Since asynchronous logic adopts distributed control scheme, the traditional methods for handling hazards in synchronous processors can not be directly applied to asynchronous processors. In this paper, the methods for dealing with data hazards and control hazards in AsynRISC are discussed.

Original languageEnglish
Title of host publication2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages1093-1096
Number of pages4
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China
Duration: 25 05 200827 05 2008

Publication series

Name2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Conference

Conference2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Country/TerritoryChina
CityXiamen, Fujian Province
Period25/05/0827/05/08

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