Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification

Yan Chen; Yuan En Yu; Yu Cheng Lin; Chih Hung Hsieh; Muh Tian Shiue; Chih Feng Wu

doi:10.1109/ICCE-TW.2015.7216860

Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification

Yan Chen, Yuan En Yu, Yu Cheng Lin, Chih Hung Hsieh, Muh Tian Shiue, Chih Feng Wu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we focus on the design of digital baseband inner receiver for Power Line Communication (PLC) system based on IEEE P1901 specification. The baseband receiver is composed of digital received filter, synchronization, fast Fourier transform (FFT), channel estimation/equalization and timing frequency offset (TFO) synchronization. The baseband receiver provides the throughput rate of 170 Mbps with 1024-QAM constellation. The chip is designed with 90 nm CMOS process. The core area is 2.071×2.071 mm² with the power consumption of 89.9 mW at the supply voltage of 1.0 V.

Original language	English
Title of host publication	2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	210-211
Number of pages	2
ISBN (Electronic)	9781479987443
DOIs	https://doi.org/10.1109/ICCE-TW.2015.7216860
State	Published - 20 08 2015
Externally published	Yes
Event	2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 - Taipei, Taiwan Duration: 06 06 2015 → 08 06 2015

Publication series

Name	2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Conference

Conference	2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
Country/Territory	Taiwan
City	Taipei
Period	06/06/15 → 08/06/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

Baseband
Channel estimation
Layout
Least squares approximations
OFDM
Receivers
Synchronization

Access to Document

10.1109/ICCE-TW.2015.7216860

Cite this

Chen, Y., Yu, Y. E., Lin, Y. C., Hsieh, C. H., Shiue, M. T., & Wu, C. F. (2015). Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification. In 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 (pp. 210-211). Article 7216860 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE-TW.2015.7216860

Chen, Yan ; Yu, Yuan En ; Lin, Yu Cheng et al. / Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification. 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 210-211 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015).

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title = "Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification",

abstract = "In this paper, we focus on the design of digital baseband inner receiver for Power Line Communication (PLC) system based on IEEE P1901 specification. The baseband receiver is composed of digital received filter, synchronization, fast Fourier transform (FFT), channel estimation/equalization and timing frequency offset (TFO) synchronization. The baseband receiver provides the throughput rate of 170 Mbps with 1024-QAM constellation. The chip is designed with 90 nm CMOS process. The core area is 2.071×2.071 mm2 with the power consumption of 89.9 mW at the supply voltage of 1.0 V.",

keywords = "Baseband, Channel estimation, Layout, Least squares approximations, OFDM, Receivers, Synchronization",

author = "Yan Chen and Yu, {Yuan En} and Lin, {Yu Cheng} and Hsieh, {Chih Hung} and Shiue, {Muh Tian} and Wu, {Chih Feng}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 ; Conference date: 06-06-2015 Through 08-06-2015",

year = "2015",

month = aug,

day = "20",

doi = "10.1109/ICCE-TW.2015.7216860",

language = "英语",

series = "2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "210--211",

booktitle = "2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015",

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}

Chen, Y, Yu, YE, Lin, YC, Hsieh, CH, Shiue, MT & Wu, CF 2015, Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification. in 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015., 7216860, 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015, Institute of Electrical and Electronics Engineers Inc., pp. 210-211, 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015, Taipei, Taiwan, 06/06/15. https://doi.org/10.1109/ICCE-TW.2015.7216860

Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification. / Chen, Yan; Yu, Yuan En; Lin, Yu Cheng et al.
2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 210-211 7216860 (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification

AU - Chen, Yan

AU - Yu, Yuan En

AU - Lin, Yu Cheng

AU - Hsieh, Chih Hung

AU - Shiue, Muh Tian

AU - Wu, Chih Feng

PY - 2015/8/20

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N2 - In this paper, we focus on the design of digital baseband inner receiver for Power Line Communication (PLC) system based on IEEE P1901 specification. The baseband receiver is composed of digital received filter, synchronization, fast Fourier transform (FFT), channel estimation/equalization and timing frequency offset (TFO) synchronization. The baseband receiver provides the throughput rate of 170 Mbps with 1024-QAM constellation. The chip is designed with 90 nm CMOS process. The core area is 2.071×2.071 mm2 with the power consumption of 89.9 mW at the supply voltage of 1.0 V.

AB - In this paper, we focus on the design of digital baseband inner receiver for Power Line Communication (PLC) system based on IEEE P1901 specification. The baseband receiver is composed of digital received filter, synchronization, fast Fourier transform (FFT), channel estimation/equalization and timing frequency offset (TFO) synchronization. The baseband receiver provides the throughput rate of 170 Mbps with 1024-QAM constellation. The chip is designed with 90 nm CMOS process. The core area is 2.071×2.071 mm2 with the power consumption of 89.9 mW at the supply voltage of 1.0 V.

KW - Baseband

KW - Channel estimation

KW - Layout

KW - Least squares approximations

KW - OFDM

KW - Receivers

KW - Synchronization

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BT - 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Y2 - 6 June 2015 through 8 June 2015

ER -

Chen Y, Yu YE, Lin YC, Hsieh CH, Shiue MT, Wu CF. Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification. In 2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 210-211. 7216860. (2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015). doi: 10.1109/ICCE-TW.2015.7216860

Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification

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Keywords

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