Design of easily testable VLSI arrays for discrete cosine transform

Shyue Kung Lu; Cheng Wen Wu; Sy Yen Kuo

doi:10.1109/ACSSC.1992.269072

Design of easily testable VLSI arrays for discrete cosine transform

Shyue Kung Lu
, Cheng Wen Wu
, Sy Yen Kuo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A design-for-testability approach based on die M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT). Our M-testability conditions guarantee 100% single-cellfault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. Apart from the cell-fault model, we also discuss the DCT array testing using die module-fault model. This method detects all possible combinational module faults pseudoexhaustively. Since practical DCT arrays can be quite large, diagnosis for the array is considered important. We propose an off-line fault diagnosis scheme which detects and locates any faulty module by a self-comparison approach.

Original language	English
Title of host publication	Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
Publisher	IEEE Computer Society
Pages	989-993
Number of pages	5
ISBN (Electronic)	0818631600
DOIs	https://doi.org/10.1109/ACSSC.1992.269072
State	Published - 1992
Externally published	Yes
Event	26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 - Pacific Grove, United States Duration: 26 10 1992 → 28 10 1992

Publication series

Name	Conference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)	1058-6393

Conference

Conference	26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992
Country/Territory	United States
City	Pacific Grove
Period	26/10/92 → 28/10/92

Bibliographical note

Publisher Copyright:
© 1992 IEEE.

Keywords

Design for testability
Discrete cosine transform
Iterative logic array
Systolic array
Testing

Access to Document

10.1109/ACSSC.1992.269072

Cite this

Lu, S. K., Wu, C. W., & Kuo, S. Y. (1992). Design of easily testable VLSI arrays for discrete cosine transform. In Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 (pp. 989-993). Article 269072 (Conference Record - Asilomar Conference on Signals, Systems and Computers). IEEE Computer Society. https://doi.org/10.1109/ACSSC.1992.269072

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title = "Design of easily testable VLSI arrays for discrete cosine transform",

abstract = "A design-for-testability approach based on die M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT). Our M-testability conditions guarantee 100\% single-cellfault testability with a minimum number of test patterns. A hardware overhead of no more than 6\% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. Apart from the cell-fault model, we also discuss the DCT array testing using die module-fault model. This method detects all possible combinational module faults pseudoexhaustively. Since practical DCT arrays can be quite large, diagnosis for the array is considered important. We propose an off-line fault diagnosis scheme which detects and locates any faulty module by a self-comparison approach.",

keywords = "Design for testability, Discrete cosine transform, Iterative logic array, Systolic array, Testing",

author = "Lu, \{Shyue Kung\} and Wu, \{Cheng Wen\} and Kuo, \{Sy Yen\}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992 ; Conference date: 26-10-1992 Through 28-10-1992",

year = "1992",

doi = "10.1109/ACSSC.1992.269072",

language = "英语",

series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",

publisher = "IEEE Computer Society",

pages = "989--993",

booktitle = "Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992",

address = "美国",

}

Lu, SK, Wu, CW & Kuo, SY 1992, Design of easily testable VLSI arrays for discrete cosine transform. in Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992., 269072, Conference Record - Asilomar Conference on Signals, Systems and Computers, IEEE Computer Society, pp. 989-993, 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992, Pacific Grove, United States, 26/10/92. https://doi.org/10.1109/ACSSC.1992.269072

Design of easily testable VLSI arrays for discrete cosine transform. / Lu, Shyue Kung; Wu, Cheng Wen; Kuo, Sy Yen.
Conference Record of the 26th Asilomar Conference on Signals, Systems and Computers, ACSSC 1992. IEEE Computer Society, 1992. p. 989-993 269072 (Conference Record - Asilomar Conference on Signals, Systems and Computers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wu, Cheng Wen

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N2 - A design-for-testability approach based on die M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT). Our M-testability conditions guarantee 100% single-cellfault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. Apart from the cell-fault model, we also discuss the DCT array testing using die module-fault model. This method detects all possible combinational module faults pseudoexhaustively. Since practical DCT arrays can be quite large, diagnosis for the array is considered important. We propose an off-line fault diagnosis scheme which detects and locates any faulty module by a self-comparison approach.

AB - A design-for-testability approach based on die M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT). Our M-testability conditions guarantee 100% single-cellfault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. Apart from the cell-fault model, we also discuss the DCT array testing using die module-fault model. This method detects all possible combinational module faults pseudoexhaustively. Since practical DCT arrays can be quite large, diagnosis for the array is considered important. We propose an off-line fault diagnosis scheme which detects and locates any faulty module by a self-comparison approach.

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KW - Discrete cosine transform

KW - Iterative logic array

KW - Systolic array

KW - Testing

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ER -

Design of easily testable VLSI arrays for discrete cosine transform

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Keywords

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