| Translated title of the contribution | 改善測試面積及功率消耗之周邊電路設計 |
|---|---|
| Original language | American English |
| Supervisors/Advisors |
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| State | Published - 2005 |
| Externally published | Yes |
Design Wrapper with Low Area and Test Power Consumption
葉家瑋
Research output: Types of Thesis › Master's thesis