Device performance improvement of InGaP/InGaAs doped-channel FETs

Feng Tso Chien*, Jin Mu Yin, Hsien Chin Chiu, Yi Jen Chan

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

6 Scopus citations

Abstract

Partial drain/source ohmic recess InGaP/InGaAs/GaAs doped-channel field-effect transistors (OR-DCFETs) are proposed and fabricated in this study. The proposed ohmic recess process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer and therefore improves the device performance in terms of dc and source resistance, as well as RF characteristics. We compare the proposed devices with the DCFETs using the conventional process by means of experiments, where the Yang-Long method is used to analyze the effect of parasitic source resistances.

Original languageEnglish
Pages (from-to)861-863
Number of pages3
JournalIEEE Electron Device Letters
Volume26
Issue number12
DOIs
StatePublished - 12 2005

Keywords

  • Doped-channel field-effect transistors (DCFETs)
  • InGaP-InGaAs
  • Ohmic recess
  • Source and drain resistance

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