Digital VLSI Multiprocessor Design for Neurocomputers

Chia Fen Chang; Bing J. Sheu

doi:10.1109/IJCNN.1992.226993

Digital VLSI Multiprocessor Design for Neurocomputers

Chia Fen Chang
, Bing J. Sheu

University of Southern California

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The architecture and circuit design of digital processors for general-purpose neurocomputing are presented. The processing element is suitable for a tightly coupled multiprocessor chip connected in 1-dimensional ring or 2-dimensional mesh fashion. An off-chip microprogrammed array controller broadcasts instructions to all processing elements. Mappings of the feedforward and feedback operations in the back-propagation neural network into the mesh-connected processing element matrix are described. Detailed design of the circuit blocks is also described. More than 128 processing elements can be implemented in a super chip through the advanced 0.5-μm CMOS technology from TRW Inc. to achieve 2.56 billion operations per second. The multiprocessor chip can be used for various types of neural networks including back-propagation multilayer networks and self-organizing networks.

Original language	English
Title of host publication	Proceedings - 1992 International Joint Conference on Neural Networks, IJCNN 1992
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-6
Number of pages	6
ISBN (Electronic)	0780305590
DOIs	https://doi.org/10.1109/IJCNN.1992.226993
State	Published - 1992
Externally published	Yes
Event	1992 International Joint Conference on Neural Networks, IJCNN 1992 - Baltimore, United States Duration: 07 06 1992 → 11 06 1992

Publication series

Name	Proceedings of the International Joint Conference on Neural Networks
Volume	2

Conference

Conference	1992 International Joint Conference on Neural Networks, IJCNN 1992
Country/Territory	United States
City	Baltimore
Period	07/06/92 → 11/06/92

Bibliographical note

Publisher Copyright:
© 1992 IEEE

Access to Document

10.1109/IJCNN.1992.226993

Cite this

@inproceedings{c0952839b53d4fc2b89cc6c169f71fc7,

title = "Digital VLSI Multiprocessor Design for Neurocomputers",

abstract = "The architecture and circuit design of digital processors for general-purpose neurocomputing are presented. The processing element is suitable for a tightly coupled multiprocessor chip connected in 1-dimensional ring or 2-dimensional mesh fashion. An off-chip microprogrammed array controller broadcasts instructions to all processing elements. Mappings of the feedforward and feedback operations in the back-propagation neural network into the mesh-connected processing element matrix are described. Detailed design of the circuit blocks is also described. More than 128 processing elements can be implemented in a super chip through the advanced 0.5-μm CMOS technology from TRW Inc. to achieve 2.56 billion operations per second. The multiprocessor chip can be used for various types of neural networks including back-propagation multilayer networks and self-organizing networks.",

author = "Chang, \{Chia Fen\} and Sheu, \{Bing J.\}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE; 1992 International Joint Conference on Neural Networks, IJCNN 1992 ; Conference date: 07-06-1992 Through 11-06-1992",

year = "1992",

doi = "10.1109/IJCNN.1992.226993",

language = "英语",

series = "Proceedings of the International Joint Conference on Neural Networks",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--6",

booktitle = "Proceedings - 1992 International Joint Conference on Neural Networks, IJCNN 1992",

address = "美国",

}

Chang, CF & Sheu, BJ 1992, Digital VLSI Multiprocessor Design for Neurocomputers. in Proceedings - 1992 International Joint Conference on Neural Networks, IJCNN 1992. Proceedings of the International Joint Conference on Neural Networks, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 1-6, 1992 International Joint Conference on Neural Networks, IJCNN 1992, Baltimore, United States, 07/06/92. https://doi.org/10.1109/IJCNN.1992.226993

Digital VLSI Multiprocessor Design for Neurocomputers. / Chang, Chia Fen; Sheu, Bing J.
Proceedings - 1992 International Joint Conference on Neural Networks, IJCNN 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1-6 (Proceedings of the International Joint Conference on Neural Networks; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Digital VLSI Multiprocessor Design for Neurocomputers

AU - Chang, Chia Fen

AU - Sheu, Bing J.

PY - 1992

Y1 - 1992

N2 - The architecture and circuit design of digital processors for general-purpose neurocomputing are presented. The processing element is suitable for a tightly coupled multiprocessor chip connected in 1-dimensional ring or 2-dimensional mesh fashion. An off-chip microprogrammed array controller broadcasts instructions to all processing elements. Mappings of the feedforward and feedback operations in the back-propagation neural network into the mesh-connected processing element matrix are described. Detailed design of the circuit blocks is also described. More than 128 processing elements can be implemented in a super chip through the advanced 0.5-μm CMOS technology from TRW Inc. to achieve 2.56 billion operations per second. The multiprocessor chip can be used for various types of neural networks including back-propagation multilayer networks and self-organizing networks.

AB - The architecture and circuit design of digital processors for general-purpose neurocomputing are presented. The processing element is suitable for a tightly coupled multiprocessor chip connected in 1-dimensional ring or 2-dimensional mesh fashion. An off-chip microprogrammed array controller broadcasts instructions to all processing elements. Mappings of the feedforward and feedback operations in the back-propagation neural network into the mesh-connected processing element matrix are described. Detailed design of the circuit blocks is also described. More than 128 processing elements can be implemented in a super chip through the advanced 0.5-μm CMOS technology from TRW Inc. to achieve 2.56 billion operations per second. The multiprocessor chip can be used for various types of neural networks including back-propagation multilayer networks and self-organizing networks.

UR - https://www.scopus.com/pages/publications/30244452547

U2 - 10.1109/IJCNN.1992.226993

DO - 10.1109/IJCNN.1992.226993

M3 - 会议稿件

AN - SCOPUS:30244452547

T3 - Proceedings of the International Joint Conference on Neural Networks

SP - 1

EP - 6

BT - Proceedings - 1992 International Joint Conference on Neural Networks, IJCNN 1992

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1992 International Joint Conference on Neural Networks, IJCNN 1992

Y2 - 7 June 1992 through 11 June 1992

ER -

Digital VLSI Multiprocessor Design for Neurocomputers

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Bibliographical note

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