| Translated title of the contribution | 積體電路保護層的最佳化以改善漏電流及 DRAM 資料的保持時間 |
|---|---|
| Original language | American English |
| Supervisors/Advisors |
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| State | Published - 2004 |
| Externally published | Yes |
DRAM Leakage Current and Retention Time Improvement by Back-end Passivation Film Optimization
吳昌榮
Research output: Types of Thesis › Master's thesis