Duty cycle control circuit and applications to frequency dividers

Hwang Cherng Chow*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

A duty cycle control circuit for clock signals is presented. The proposed circuit uses a rising edge detector to generate one shot output signals which have the same frequency of the input clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses. By using the feedback control voltage from an operational amplifier, the pulse width of generated rectangular pulses is automatically adjusted to a pre-set duty cycle. As compared to prior arts, features of this proposed circuit include simple design, low cost and less power. Furthermore, a novel design approach for frequency dividers by the proposed duty cycle control circuit is also demonstrated.

Original languageEnglish
Title of host publicationProceedings of ICECS 1999 - 6th IEEE International Conference on Electronics, Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1619-1622
Number of pages4
ISBN (Electronic)0780356829
DOIs
StatePublished - 1999
Event6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 - Pafos, Cyprus
Duration: 05 09 199908 09 1999

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3

Conference

Conference6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999
Country/TerritoryCyprus
CityPafos
Period05/09/9908/09/99

Bibliographical note

Publisher Copyright:
© 1999 IEEE.

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