Abstract
ΔVF test is a common electrical test in power diode industry for the evaluation of the integrity of solder contact between the leads and the dice. Whereas the test is effective to detect devices with voids in solder, it is found that the test is not possible to detect devices with solder under-coverage. A finite element (FE) analysis is performed to understand the effect of solder under-coverage on the thermal resistance. Both the simulation results and the experimental results will be shown in this work. A novel method to detect the solder under-coverage will be presented, and the results will be shown.
Original language | English |
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Title of host publication | 5th International Conference on Power Electronics and Drive Systems, PEDS 2003 - Proceedings |
Editors | King-Jet Tseng |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 38-42 |
Number of pages | 5 |
ISBN (Electronic) | 0780378857 |
DOIs | |
State | Published - 2003 |
Externally published | Yes |
Event | 5th International Conference on Power Electronics and Drive Systems, PEDS 2003 - Singapore, Singapore Duration: 17 11 2003 → 20 11 2003 |
Publication series
Name | Proceedings of the International Conference on Power Electronics and Drive Systems |
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Volume | 1 |
Conference
Conference | 5th International Conference on Power Electronics and Drive Systems, PEDS 2003 |
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Country/Territory | Singapore |
City | Singapore |
Period | 17/11/03 → 20/11/03 |
Bibliographical note
Publisher Copyright:© 2003 IEEE.
Keywords
- Power diode
- electrical resistance
- finite element analysis
- solder under-coverage
- thermal resistance