Effects of overlaying dielectric layer and its local geometry on TSV-induced KOZ in 3D IC

This study aims to investigate the effects of overlaying dielectric layer and its local geometry on keep-out zone (KOZ) induced from through-silicon via (TSV) in 3D integrated circuit packaging. Prior to the study, the saturated current changes (or related carrier mobility changes) of both n- and p-MOS transistors from the finite element simulations are validated with experimental data. After model verification, the six cases with various local dielectric structures are proposed to minimize KOZ, which is based on the more than 5% change in saturated current. It is shown that the case with embedded SiO ₂ on the top of Cu TSV has the least effect (or the minimum KOZ) on saturated current change among those cases. Furthermore, the various embedded-SiO₂ depth on the top of Cu TSV are further investigated. It is found that saturated current change of p-MOS placed in both horizontal and vertical directions on Si substrate can be minimized by using a 6-μm-deep embedded SiO₂. Besides those results, the other parameters such as the thickness of dielectric layer, and silicon crystal orientations of [110] and [100] will also be studied and discussed in this study.