Abstract
This paper describes an efficient 9-cells array architecture with data-rings for the 3-step hierarchical search block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify control scheme and reduce latency, respectively. In addition, we utilize a three-half-search-area scheme to reduce external memory access and interconnection. The results demonstrate that the array architecture with the data-rings gives short latency and low input ports. It also provides a high normalized throughput solution for the 3SHS.
| Original language | English |
|---|---|
| Pages (from-to) | 1361-1364 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| State | Published - 1997 |
| Externally published | Yes |
| Event | Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 09 06 1997 → 12 06 1997 |