Efficient MOS transistor charge/capacitance model with continuous expressions for VLSI

Steve H. Jen*, Bing J. Sheu, Alex Y. Park

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

A unified modeling approach for the submicron MOS transistor charge/capacitance characteristics in all operation regions is presented. The development of MOS charge model is based on the charge density approximation to reduce the complexity of the expression. The unified charge densities in gate, channel, and bulk are obtained with assistance of the sigmoid, hyperbola, and exponential interpolation techniques. By carrying out the integration of the charge densities along the channel area, the terminal charges associated with gate and bulk can be obtained. The non-reciprocal capacitance behavior is well realized in this model. Good agreement between the measurement data and simulation results is obtained.

Original languageEnglish
Pages (from-to)413-416
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume6
StatePublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: 31 05 199803 06 1998

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