Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering

Che Lun Hung; Po Chang Wu; Hsiao Hsi Wang; Chun Yuan Lin

doi:10.1109/HPCC-CSS-ICESS.2015.209

Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering

Che Lun Hung, Po Chang Wu, Hsiao Hsi Wang, Chun Yuan Lin

Providence University Taiwan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In the past decades, the Internet usage has increased dramatically. For the network security, the network packet filtering is an important strategy to identify malicious network packets. However, malicious attacks spread much faster than network administrators can respond. The software-only implementations of filter are unlikely to meet the performance goals. Therefore, we develop a novel GPGPU-based parallel packet classification approach by adopting bloom filter to inspect the packet payload by leveraging the computation power of GPGPU. The experiment results present that the proposed algorithm can be significantly enhanced the performance of filtering packets. According to the experimental results, the proposed method can achieve over 5.4 times speed up over the sequential bloom filter on single CPU.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1843-1847
Number of pages	5
ISBN (Electronic)	9781479989362
DOIs	https://doi.org/10.1109/HPCC-CSS-ICESS.2015.209
State	Published - 23 11 2015
Event	17th IEEE International Conference on High Performance Computing and Communications, IEEE 7th International Symposium on Cyberspace Safety and Security and IEEE 12th International Conference on Embedded Software and Systems, HPCC-ICESS-CSS 2015 - New York, United States Duration: 24 08 2015 → 26 08 2015

Publication series

Name	Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015

Conference

Conference	17th IEEE International Conference on High Performance Computing and Communications, IEEE 7th International Symposium on Cyberspace Safety and Security and IEEE 12th International Conference on Embedded Software and Systems, HPCC-ICESS-CSS 2015
Country/Territory	United States
City	New York
Period	24/08/15 → 26/08/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

GPU
Hash
Network
Packet Classfication
Parallel Computing

Access to Document

10.1109/HPCC-CSS-ICESS.2015.209

Cite this

Hung, C. L., Wu, P. C., Wang, H. H., & Lin, C. Y. (2015). Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering. In Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015 (pp. 1843-1847). Article 7336440 (Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPCC-CSS-ICESS.2015.209

Hung, Che Lun ; Wu, Po Chang ; Wang, Hsiao Hsi et al. / Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering. Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1843-1847 (Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015).

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abstract = "In the past decades, the Internet usage has increased dramatically. For the network security, the network packet filtering is an important strategy to identify malicious network packets. However, malicious attacks spread much faster than network administrators can respond. The software-only implementations of filter are unlikely to meet the performance goals. Therefore, we develop a novel GPGPU-based parallel packet classification approach by adopting bloom filter to inspect the packet payload by leveraging the computation power of GPGPU. The experiment results present that the proposed algorithm can be significantly enhanced the performance of filtering packets. According to the experimental results, the proposed method can achieve over 5.4 times speed up over the sequential bloom filter on single CPU.",

keywords = "GPU, Hash, Network, Packet Classfication, Parallel Computing",

author = "Hung, \{Che Lun\} and Wu, \{Po Chang\} and Wang, \{Hsiao Hsi\} and Lin, \{Chun Yuan\}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 17th IEEE International Conference on High Performance Computing and Communications, IEEE 7th International Symposium on Cyberspace Safety and Security and IEEE 12th International Conference on Embedded Software and Systems, HPCC-ICESS-CSS 2015 ; Conference date: 24-08-2015 Through 26-08-2015",

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Hung, CL, Wu, PC, Wang, HH & Lin, CY 2015, Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering. in Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015., 7336440, Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015, Institute of Electrical and Electronics Engineers Inc., pp. 1843-1847, 17th IEEE International Conference on High Performance Computing and Communications, IEEE 7th International Symposium on Cyberspace Safety and Security and IEEE 12th International Conference on Embedded Software and Systems, HPCC-ICESS-CSS 2015, New York, United States, 24/08/15. https://doi.org/10.1109/HPCC-CSS-ICESS.2015.209

Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering. / Hung, Che Lun; Wu, Po Chang; Wang, Hsiao Hsi et al.
Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1843-1847 7336440 (Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hung, Che Lun

AU - Wu, Po Chang

AU - Wang, Hsiao Hsi

AU - Lin, Chun Yuan

PY - 2015/11/23

Y1 - 2015/11/23

N2 - In the past decades, the Internet usage has increased dramatically. For the network security, the network packet filtering is an important strategy to identify malicious network packets. However, malicious attacks spread much faster than network administrators can respond. The software-only implementations of filter are unlikely to meet the performance goals. Therefore, we develop a novel GPGPU-based parallel packet classification approach by adopting bloom filter to inspect the packet payload by leveraging the computation power of GPGPU. The experiment results present that the proposed algorithm can be significantly enhanced the performance of filtering packets. According to the experimental results, the proposed method can achieve over 5.4 times speed up over the sequential bloom filter on single CPU.

AB - In the past decades, the Internet usage has increased dramatically. For the network security, the network packet filtering is an important strategy to identify malicious network packets. However, malicious attacks spread much faster than network administrators can respond. The software-only implementations of filter are unlikely to meet the performance goals. Therefore, we develop a novel GPGPU-based parallel packet classification approach by adopting bloom filter to inspect the packet payload by leveraging the computation power of GPGPU. The experiment results present that the proposed algorithm can be significantly enhanced the performance of filtering packets. According to the experimental results, the proposed method can achieve over 5.4 times speed up over the sequential bloom filter on single CPU.

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KW - Network

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BT - Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

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Hung CL, Wu PC, Wang HH, Lin CY. Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering. In Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1843-1847. 7336440. (Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015). doi: 10.1109/HPCC-CSS-ICESS.2015.209

Efficient parallel muti-pattern matching using GPGPU acceleration for packet filtering

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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