Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu ₂O ₃ gate dielectrics

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu ₂O ₃ gate dielectric. High-κ Eu ₂O ₃ LTPS-TFT annealed at 500 °C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm ²/V-s, a small subthreshold swing of 142 mV/decade, and a high I _on/I _off current ratio of 1.34 × 10 ⁷. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu ₂O ₃ gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu ₂O ₃ LTPS-TFT device.