Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr203/SiOxN y gate dielectric

Tune Ming Pan; Tin Wei Wu; Ching Lin Chan; Kai Ming Chen; Chih Hong Lee

doi:10.1149/1.2911494

Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric

Tune Ming Pan^*, Tin Wei Wu, Ching Lin Chan, Kai Ming Chen, Chih Hong Lee

^*Corresponding author for this work

Chang Gung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, we have developed a stacked Pr₂O ₃/SiO_xN_y gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high I_on/I_off current ratio. This phenomenon is attributed to the smooth Pr₂O₃/poly-Si interface and the low interface trap density provided by N₂O plasma treatment. The presence of an SiO_xN_y buffer layer also enhanced the electrical reliability of the Pr₂O₃/poly-Si TFT. All of these results suggest that a high-k Pr₂O₃ gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

Original language	English
Title of host publication	ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4
Subtitle of host publication	New Materials, Processes, and Equipment
Pages	151-155
Number of pages	5
Edition	1
DOIs	https://doi.org/10.1149/1.2911494
State	Published - 2008
Event	Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4 - Phoenix, AZ, United States Duration: 18 05 2008 → 22 05 2008

Publication series

Name	ECS Transactions
Number	1
Volume	13
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4
Country/Territory	United States
City	Phoenix, AZ
Period	18/05/08 → 22/05/08

Access to Document

10.1149/1.2911494

Cite this

Pan, T. M., Wu, T. W., Chan, C. L., Chen, K. M., & Lee, C. H. (2008). Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment (1 ed., pp. 151-155). (ECS Transactions; Vol. 13, No. 1). https://doi.org/10.1149/1.2911494

Pan, Tune Ming ; Wu, Tin Wei ; Chan, Ching Lin et al. / Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1. ed. 2008. pp. 151-155 (ECS Transactions; 1).

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title = "Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr203/SiOxN y gate dielectric",

abstract = "In this paper, we have developed a stacked Pr2O 3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high Ion/Ioff current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.",

author = "Pan, {Tune Ming} and Wu, {Tin Wei} and Chan, {Ching Lin} and Chen, {Kai Ming} and Lee, {Chih Hong}",

year = "2008",

doi = "10.1149/1.2911494",

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series = "ECS Transactions",

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pages = "151--155",

booktitle = "ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4",

edition = "1",

note = "Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4 ; Conference date: 18-05-2008 Through 22-05-2008",

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Pan, TM, Wu, TW, Chan, CL, Chen, KM & Lee, CH 2008, Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. in ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1 edn, ECS Transactions, no. 1, vol. 13, pp. 151-155, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4, Phoenix, AZ, United States, 18/05/08. https://doi.org/10.1149/1.2911494

Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. / Pan, Tune Ming; Wu, Tin Wei; Chan, Ching Lin et al.
ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1. ed. 2008. p. 151-155 (ECS Transactions; Vol. 13, No. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, we have developed a stacked Pr2O 3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high Ion/Ioff current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

AB - In this paper, we have developed a stacked Pr2O 3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high Ion/Ioff current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

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Pan TM, Wu TW, Chan CL, Chen KM, Lee CH. Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1 ed. 2008. p. 151-155. (ECS Transactions; 1). doi: 10.1149/1.2911494