Enabling circuit design using FinFETs through close ecosystem collaboration

Bing J. Sheu, Chih Sheng Chang, Yen Huei Chen, Ken Wang, Kuo Ji Chen, Yung Chow Peng, Li Chun Tien, Ming Hsiang Song, Cliff Hou, Jack Yuan Chen Sun, Chenming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes key issues in enabling circuit design using FinFETs and how to address them effectively.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
PagesT110-T111
StatePublished - 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 12 06 201314 06 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2013 Symposium on VLSI Circuits, VLSIC 2013
Country/TerritoryJapan
CityKyoto
Period12/06/1314/06/13

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