Energy-Aware Compiler Optimization for VLIW-DSP Cores

Yung Cheng Ma; Tse An Liu; Wen Shih Chao

doi:10.1007/978-3-642-35473-1_77

Energy-Aware Compiler Optimization for VLIW-DSP Cores

Yung Cheng Ma^*
, Tse An Liu
, Wen Shih Chao

^*Corresponding author for this work

Department of Computer Science and Information Engineering

Chang Gung University

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

2 Scopus citations

Abstract

VLIW-DSP processor cores are widely used in embedded SoCs. Improving the energy efficiency becomes one of the key issues in designing a VLIW-DSP core. This paper proposes compiler optimization algorithms to reduce the register file power in a VLIW-DSP processor. The optimization is targeted to VLIW processors in which each execution slot is associated with a low-powered local register file. Instruction scheduling and register allocation algorithms are proposed to direct operand accesses to the local register files. We propose energyaware list scheduling algorithm to reduce cross-slot data dependencies without affecting the program execution time. Constrained by the instruction scheduling result, energy-aware register allocation is performed through weighted graph coloring. Evaluation with MiBench benchmark suite shows that our approach reduces over 50% of data transfer energy with low hardware cost. This research shows a cost-effective way to design an energy-efficient VLIW- DSP processor.

Original language	English
Title of host publication	Advances in Intelligent Systems and Applications - Volume 2
Subtitle of host publication	Proceedings of the International Computer
Editors	Chang Ruay-Shiung, Peng Sheng-Lung, Lin Chia-Chen
Pages	779-788
Number of pages	10
DOIs	https://doi.org/10.1007/978-3-642-35473-1_77
State	Published - 2013

Publication series

Name	Smart Innovation, Systems and Technologies
Volume	21
ISSN (Print)	2190-3018
ISSN (Electronic)	2190-3026

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Energy-aware instruction scheduling
Register allocation
VLIW-DSP processor
Weighted graph coloring

Access to Document

10.1007/978-3-642-35473-1_77

Cite this

Ma, Y. C., Liu, T. A., & Chao, W. S. (2013). Energy-Aware Compiler Optimization for VLIW-DSP Cores. In C. Ruay-Shiung, P. Sheng-Lung, & L. Chia-Chen (Eds.), Advances in Intelligent Systems and Applications - Volume 2: Proceedings of the International Computer (pp. 779-788). (Smart Innovation, Systems and Technologies; Vol. 21). https://doi.org/10.1007/978-3-642-35473-1_77

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abstract = "VLIW-DSP processor cores are widely used in embedded SoCs. Improving the energy efficiency becomes one of the key issues in designing a VLIW-DSP core. This paper proposes compiler optimization algorithms to reduce the register file power in a VLIW-DSP processor. The optimization is targeted to VLIW processors in which each execution slot is associated with a low-powered local register file. Instruction scheduling and register allocation algorithms are proposed to direct operand accesses to the local register files. We propose energyaware list scheduling algorithm to reduce cross-slot data dependencies without affecting the program execution time. Constrained by the instruction scheduling result, energy-aware register allocation is performed through weighted graph coloring. Evaluation with MiBench benchmark suite shows that our approach reduces over 50\% of data transfer energy with low hardware cost. This research shows a cost-effective way to design an energy-efficient VLIW- DSP processor.",

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Energy-Aware Compiler Optimization for VLIW-DSP Cores. / Ma, Yung Cheng; Liu, Tse An; Chao, Wen Shih.
Advances in Intelligent Systems and Applications - Volume 2: Proceedings of the International Computer. ed. / Chang Ruay-Shiung; Peng Sheng-Lung; Lin Chia-Chen. 2013. p. 779-788 (Smart Innovation, Systems and Technologies; Vol. 21).

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

TY - CHAP

T1 - Energy-Aware Compiler Optimization for VLIW-DSP Cores

AU - Ma, Yung Cheng

AU - Liu, Tse An

AU - Chao, Wen Shih

PY - 2013

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N2 - VLIW-DSP processor cores are widely used in embedded SoCs. Improving the energy efficiency becomes one of the key issues in designing a VLIW-DSP core. This paper proposes compiler optimization algorithms to reduce the register file power in a VLIW-DSP processor. The optimization is targeted to VLIW processors in which each execution slot is associated with a low-powered local register file. Instruction scheduling and register allocation algorithms are proposed to direct operand accesses to the local register files. We propose energyaware list scheduling algorithm to reduce cross-slot data dependencies without affecting the program execution time. Constrained by the instruction scheduling result, energy-aware register allocation is performed through weighted graph coloring. Evaluation with MiBench benchmark suite shows that our approach reduces over 50% of data transfer energy with low hardware cost. This research shows a cost-effective way to design an energy-efficient VLIW- DSP processor.

AB - VLIW-DSP processor cores are widely used in embedded SoCs. Improving the energy efficiency becomes one of the key issues in designing a VLIW-DSP core. This paper proposes compiler optimization algorithms to reduce the register file power in a VLIW-DSP processor. The optimization is targeted to VLIW processors in which each execution slot is associated with a low-powered local register file. Instruction scheduling and register allocation algorithms are proposed to direct operand accesses to the local register files. We propose energyaware list scheduling algorithm to reduce cross-slot data dependencies without affecting the program execution time. Constrained by the instruction scheduling result, energy-aware register allocation is performed through weighted graph coloring. Evaluation with MiBench benchmark suite shows that our approach reduces over 50% of data transfer energy with low hardware cost. This research shows a cost-effective way to design an energy-efficient VLIW- DSP processor.

KW - Energy-aware instruction scheduling

KW - Register allocation

KW - VLIW-DSP processor

KW - Weighted graph coloring

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M3 - 章节

SN - 9783642354724

T3 - Smart Innovation, Systems and Technologies

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BT - Advances in Intelligent Systems and Applications - Volume 2

A2 - Ruay-Shiung, Chang

A2 - Sheng-Lung, Peng

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ER -

Energy-Aware Compiler Optimization for VLIW-DSP Cores

Abstract

Publication series

UN SDGs

Keywords

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