Enhancing boosting with semantic register in a superscalar processor

Feipei Lai; Meng Chou Chang

Enhancing boosting with semantic register in a superscalar processor

Feipei Lai^*
, Meng Chou Chang

^*Corresponding author for this work

National Taiwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

IAS-S Supports boosting with 'semantic register' and boosting boundary register to remove the dependences caused by conditional branches. In IAS-S, there is no dedicated shadow register file, and multiple levels of boosting is supported without multiple copies of register files. Any general-purpose register in IAS-S can be regarded as a sequential register or a shadow register flexibly. Furthermore, multi-way jump mechanism is combined with boosting to reduce the penalty due to frequent control transfers.

Original language	English
Title of host publication	Proceedings of the Ninth Annual International Symposium on Computer Architecture
Publisher	Publ by ACM
Pages	430
Number of pages	1
ISBN (Print)	0897915097
State	Published - 1993
Externally published	Yes
Event	Proceedings of the 19th Annual International Symposium on Compu- ter Architecture - Gold Coast, Aust Duration: 19 05 1992 → 21 05 1992

Publication series

Name	Proceedings of the Ninth Annual International Symposium on Computer Architecture

Conference

Conference	Proceedings of the 19th Annual International Symposium on Compu- ter Architecture
City	Gold Coast, Aust
Period	19/05/92 → 21/05/92

Cite this

@inproceedings{2508d87751dc494193b19a9f8f110924,

title = "Enhancing boosting with semantic register in a superscalar processor",

abstract = "IAS-S Supports boosting with 'semantic register' and boosting boundary register to remove the dependences caused by conditional branches. In IAS-S, there is no dedicated shadow register file, and multiple levels of boosting is supported without multiple copies of register files. Any general-purpose register in IAS-S can be regarded as a sequential register or a shadow register flexibly. Furthermore, multi-way jump mechanism is combined with boosting to reduce the penalty due to frequent control transfers.",

author = "Feipei Lai and Chang, \{Meng Chou\}",

year = "1993",

language = "英语",

isbn = "0897915097",

series = "Proceedings of the Ninth Annual International Symposium on Computer Architecture",

publisher = "Publ by ACM",

pages = "430",

booktitle = "Proceedings of the Ninth Annual International Symposium on Computer Architecture",

note = "Proceedings of the 19th Annual International Symposium on Compu- ter Architecture ; Conference date: 19-05-1992 Through 21-05-1992",

}

Lai, F & Chang, MC 1993, Enhancing boosting with semantic register in a superscalar processor. in Proceedings of the Ninth Annual International Symposium on Computer Architecture. Proceedings of the Ninth Annual International Symposium on Computer Architecture, Publ by ACM, pp. 430, Proceedings of the 19th Annual International Symposium on Compu- ter Architecture, Gold Coast, Aust, 19/05/92.

Enhancing boosting with semantic register in a superscalar processor. / Lai, Feipei; Chang, Meng Chou.
Proceedings of the Ninth Annual International Symposium on Computer Architecture. Publ by ACM, 1993. p. 430 (Proceedings of the Ninth Annual International Symposium on Computer Architecture).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - IAS-S Supports boosting with 'semantic register' and boosting boundary register to remove the dependences caused by conditional branches. In IAS-S, there is no dedicated shadow register file, and multiple levels of boosting is supported without multiple copies of register files. Any general-purpose register in IAS-S can be regarded as a sequential register or a shadow register flexibly. Furthermore, multi-way jump mechanism is combined with boosting to reduce the penalty due to frequent control transfers.

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SN - 0897915097

T3 - Proceedings of the Ninth Annual International Symposium on Computer Architecture

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BT - Proceedings of the Ninth Annual International Symposium on Computer Architecture

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T2 - Proceedings of the 19th Annual International Symposium on Compu- ter Architecture

Y2 - 19 May 1992 through 21 May 1992

ER -

Enhancing boosting with semantic register in a superscalar processor

Abstract

Publication series

Conference

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