Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors

Chen Chen Yang; Yung Chen Chen; Horng Chih Lin; Ruey Dar Chang; Pei Wen Li; Tiao Yuan Huang

doi:10.1109/SNW.2016.7577987

Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors

Chen Chen Yang, Yung Chen Chen, Horng Chih Lin, Ruey Dar Chang, Pei Wen Li, Tiao Yuan Huang

Department of Electronic Engineering

National Yang Ming Chiao Tung University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (G_m). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

Original language	English
Title of host publication	2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	64-65
Number of pages	2
ISBN (Electronic)	9781509007264
DOIs	https://doi.org/10.1109/SNW.2016.7577987
State	Published - 27 09 2016
Event	21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 - Honolulu, United States Duration: 12 06 2016 → 13 06 2016

Publication series

Name	2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016

Conference

Conference	21st IEEE Silicon Nanoelectronics Workshop, SNW 2016
Country/Territory	United States
City	Honolulu
Period	12/06/16 → 13/06/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Access to Document

10.1109/SNW.2016.7577987

Cite this

Yang, C. C., Chen, Y. C., Lin, H. C., Chang, R. D., Li, P. W., & Huang, T. Y. (2016). Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. In 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016 (pp. 64-65). Article 7577987 (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW.2016.7577987

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title = "Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors",

abstract = "Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.",

author = "Yang, {Chen Chen} and Chen, {Yung Chen} and Lin, {Horng Chih} and Chang, {Ruey Dar} and Li, {Pei Wen} and Huang, {Tiao Yuan}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016 ; Conference date: 12-06-2016 Through 13-06-2016",

year = "2016",

month = sep,

day = "27",

doi = "10.1109/SNW.2016.7577987",

language = "英语",

series = "2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016",

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Yang, CC, Chen, YC, Lin, HC, Chang, RD, Li, PW & Huang, TY 2016, Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. in 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016., 7577987, 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016, Institute of Electrical and Electronics Engineers Inc., pp. 64-65, 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016, Honolulu, United States, 12/06/16. https://doi.org/10.1109/SNW.2016.7577987

Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. / Yang, Chen Chen; Chen, Yung Chen; Lin, Horng Chih et al.
2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 64-65 7577987 (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Li, Pei Wen

AU - Huang, Tiao Yuan

PY - 2016/9/27

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N2 - Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

AB - Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 21st IEEE Silicon Nanoelectronics Workshop, SNW 2016

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Yang CC, Chen YC, Lin HC, Chang RD, Li PW, Huang TY. Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors. In 2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 64-65. 7577987. (2016 IEEE Silicon Nanoelectronics Workshop, SNW 2016). doi: 10.1109/SNW.2016.7577987

Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors

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