Fabrication of omega-gated negative capacitance finfets and SRAM

P. J. Sung; C. J. Su; D. D. Lu; S. X. Luo; K. H. Kao; J. Y. Ciou; C. Y. Jao; H. S. Hsu; C. J. Wang; T. C. Hong; T. H. Liao; C. C. Fang; Y. S. Wang; H. F. Huang; J. H. Li; Y. C. Huang; F. K. Hsueh; C. T. Wu; W. C.Y. Ma; K. P. Huang; Y. J. Lee; T. S. Chao; J. Y. Li; W. F. Wu; W. K. Yeh; Y. H. Wang

doi:10.1109/VLSI-TSA.2019.8804663

Fabrication of omega-gated negative capacitance finfets and SRAM

P. J. Sung
, C. J. Su
, D. D. Lu
, S. X. Luo
, K. H. Kao
, J. Y. Ciou
, C. Y. Jao
, H. S. Hsu
, C. J. Wang
, T. C. Hong
, T. H. Liao
, C. C. Fang
, Y. S. Wang
, H. F. Huang
, J. H. Li
, Y. C. Huang
, F. K. Hsueh
, C. T. Wu
, W. C.Y. Ma
, K. P. Huang

Y. J. Lee^*, T. S. Chao, J. Y. Li, W. F. Wu, W. K. Yeh, Y. H. Wang

^*Corresponding author for this work

National Nano Device Laboratories Taiwan
National Yang Ming Chiao Tung University
National Cheng Kung University
National Sun Yat-sen University
Industrial Technology Research Institute of Taiwan
National Taiwan University
National Applied Research Laboratories Taiwan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Omega-gated negative capacitance (NC) FinFETs, CMOS inverters and SRAM are fabricated and analyzed. Forming gas annealing (FGA) is performed and found to not only enhance ferroelectricity (FE) but also the NCFET electrostatics, in terms of higher \mathrm{I}-{\mathrm{ON}}, smaller hysteresis and subthreshold slop (SS). The SS is less than 60 mV/dec for both N-FinFET and P-FinFET in this work. Moreover, the CMOS inverter shows more symmetric and larger voltage gain after FGA.

Original language	English
Title of host publication	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728109428
DOIs	https://doi.org/10.1109/VLSI-TSA.2019.8804663
State	Published - 04 2019
Externally published	Yes
Event	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, Taiwan Duration: 22 04 2019 → 25 04 2019

Publication series

Name	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Conference

Conference	2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/19 → 25/04/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Access to Document

10.1109/VLSI-TSA.2019.8804663

Cite this

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., ... Wang, Y. H. (2019). Fabrication of omega-gated negative capacitance finfets and SRAM. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 Article 8804663 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2019.8804663

@inproceedings{192a8d02670a419988eb64b252297054,

title = "Fabrication of omega-gated negative capacitance finfets and SRAM",

abstract = "Omega-gated negative capacitance (NC) FinFETs, CMOS inverters and SRAM are fabricated and analyzed. Forming gas annealing (FGA) is performed and found to not only enhance ferroelectricity (FE) but also the NCFET electrostatics, in terms of higher \textbackslash{}mathrm\{I\}-\{\textbackslash{}mathrm\{ON\}\}, smaller hysteresis and subthreshold slop (SS). The SS is less than 60 mV/dec for both N-FinFET and P-FinFET in this work. Moreover, the CMOS inverter shows more symmetric and larger voltage gain after FGA.",

author = "Sung, \{P. J.\} and Su, \{C. J.\} and Lu, \{D. D.\} and Luo, \{S. X.\} and Kao, \{K. H.\} and Ciou, \{J. Y.\} and Jao, \{C. Y.\} and Hsu, \{H. S.\} and Wang, \{C. J.\} and Hong, \{T. C.\} and Liao, \{T. H.\} and Fang, \{C. C.\} and Wang, \{Y. S.\} and Huang, \{H. F.\} and Li, \{J. H.\} and Huang, \{Y. C.\} and Hsueh, \{F. K.\} and Wu, \{C. T.\} and Ma, \{W. C.Y.\} and Huang, \{K. P.\} and Lee, \{Y. J.\} and Chao, \{T. S.\} and Li, \{J. Y.\} and Wu, \{W. F.\} and Yeh, \{W. K.\} and Wang, \{Y. H.\}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 ; Conference date: 22-04-2019 Through 25-04-2019",

year = "2019",

month = apr,

doi = "10.1109/VLSI-TSA.2019.8804663",

language = "英语",

series = "2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019",

address = "美国",

}

Sung, PJ, Su, CJ, Lu, DD, Luo, SX, Kao, KH, Ciou, JY, Jao, CY, Hsu, HS, Wang, CJ, Hong, TC, Liao, TH, Fang, CC, Wang, YS, Huang, HF, Li, JH, Huang, YC, Hsueh, FK, Wu, CT, Ma, WCY, Huang, KP, Lee, YJ, Chao, TS, Li, JY, Wu, WF, Yeh, WK & Wang, YH 2019, Fabrication of omega-gated negative capacitance finfets and SRAM. in 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019., 8804663, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, Hsinchu, Taiwan, 22/04/19. https://doi.org/10.1109/VLSI-TSA.2019.8804663

Fabrication of omega-gated negative capacitance finfets and SRAM. / Sung, P. J.; Su, C. J.; Lu, D. D. et al.
2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8804663 (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fabrication of omega-gated negative capacitance finfets and SRAM

AU - Sung, P. J.

AU - Su, C. J.

AU - Lu, D. D.

AU - Luo, S. X.

AU - Kao, K. H.

AU - Ciou, J. Y.

AU - Jao, C. Y.

AU - Hsu, H. S.

AU - Wang, C. J.

AU - Hong, T. C.

AU - Liao, T. H.

AU - Fang, C. C.

AU - Wang, Y. S.

AU - Huang, H. F.

AU - Li, J. H.

AU - Huang, Y. C.

AU - Hsueh, F. K.

AU - Wu, C. T.

AU - Ma, W. C.Y.

AU - Huang, K. P.

AU - Lee, Y. J.

AU - Chao, T. S.

AU - Li, J. Y.

AU - Wu, W. F.

AU - Yeh, W. K.

AU - Wang, Y. H.

PY - 2019/4

Y1 - 2019/4

N2 - Omega-gated negative capacitance (NC) FinFETs, CMOS inverters and SRAM are fabricated and analyzed. Forming gas annealing (FGA) is performed and found to not only enhance ferroelectricity (FE) but also the NCFET electrostatics, in terms of higher \mathrm{I}-{\mathrm{ON}}, smaller hysteresis and subthreshold slop (SS). The SS is less than 60 mV/dec for both N-FinFET and P-FinFET in this work. Moreover, the CMOS inverter shows more symmetric and larger voltage gain after FGA.

AB - Omega-gated negative capacitance (NC) FinFETs, CMOS inverters and SRAM are fabricated and analyzed. Forming gas annealing (FGA) is performed and found to not only enhance ferroelectricity (FE) but also the NCFET electrostatics, in terms of higher \mathrm{I}-{\mathrm{ON}}, smaller hysteresis and subthreshold slop (SS). The SS is less than 60 mV/dec for both N-FinFET and P-FinFET in this work. Moreover, the CMOS inverter shows more symmetric and larger voltage gain after FGA.

UR - https://www.scopus.com/pages/publications/85072101546

U2 - 10.1109/VLSI-TSA.2019.8804663

DO - 10.1109/VLSI-TSA.2019.8804663

M3 - 会议稿件

AN - SCOPUS:85072101546

T3 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

BT - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Y2 - 22 April 2019 through 25 April 2019

ER -

Sung PJ, Su CJ, Lu DD, Luo SX, Kao KH, Ciou JY et al. Fabrication of omega-gated negative capacitance finfets and SRAM. In 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019). doi: 10.1109/VLSI-TSA.2019.8804663

Fabrication of omega-gated negative capacitance finfets and SRAM

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