Fast locking adaptive PLL using Dual-Edge Phase-Frequency Detector

Three-stage PLL with a Dual-Edge Phase-frequency Detector (DE-PFD) is proposed to reduce the locking time and to reduce jitter when locked. The DE-PFD speeds up the locking time by detecting the phase difference between the reference clock signal and the PLL's feedback signal of the divider circuit in both the rising edge and the falling edge. Meanwhile, the control signal generated from the DE-PFD can switch the loop bandwidth automatically. The locking status detection using DE-PFD saves the hardware overhead and switches the bandwidth smoothly. The DE-PFD is switched to the single-edge PFD to decrease the jitter further when the PLL is locked. The implemented proposed three-stage 1.6 GHz PLL under the TSMC 0.18 μm CMOS process shows the pre-simulation result of 56% locking time improvement as compared to the conventional PLL and the measured results of the RMS jitter reduced from 13.36 to 11 ps and the peak-to-peak jitter from 60 ps to 44 ps. When the bandwidth switching mechanism is activated, the power level of interference is reduced by 10 dBm.