Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's

Reconfigurable logic and memory structures are an important means of increasing manufacturing yield as both circuit density and chip size continue to increase. Yield enhancement through reconfiguration, however, necessarily relies on accurate diagnosis of fault locations. Although a substantial body of literature exists concerning testing of logic arrays, little is known regarding diagnosis of the specific locations of multiple faults in such arrays. In this paper a fault diagnosis algorithm is presented for large PLA’s.