Abstract
This article describes various techniques for fault tolerance that can be applied to systolic array architectures. The approach of algorithm-based fault tolerance is shown to be the natural one for such systems.
| Original language | English |
|---|---|
| Pages | 65-75 |
| Number of pages | 11 |
| Volume | 20 |
| No | 7 |
| Specialist publication | Computer |
| DOIs | |
| State | Published - 07 1987 |
| Externally published | Yes |