Abstract
In this work, we demonstrate vertically stacked heterogeneous dual-workfunction gate complementary FET (CFET) inverters and 6T-SRAM with n-Type IGZO and p-Type polysilicon channels for the first time. The dual-workfunction gate structure with adjusted gate biasing allows the adjustment of channel potential to match the threshold voltage of transistors for CMOS and SRAM operation. High-frequency IGZO RF devices with p-Type silicon isolation are fabricated simultaneously with the same process. Novel etching process based on fluorine-based gas with an extremely high-etching selectivity between the source/drain metal and the IGZO facilitates the definition of the source/drain region. IGZO surface treated with fluorine-based gas during over-etching step allows a low leakage current shallow passivation layer to optimize direct current characteristics.
| Original language | English |
|---|---|
| Title of host publication | 2021 IEEE International Electron Devices Meeting, IEDM 2021 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 34.4.1-34.4.4 |
| ISBN (Electronic) | 9781665425728 |
| DOIs | |
| State | Published - 2021 |
| Externally published | Yes |
| Event | 2021 IEEE International Electron Devices Meeting, IEDM 2021 - San Francisco, United States Duration: 11 12 2021 → 16 12 2021 |
Publication series
| Name | Technical Digest - International Electron Devices Meeting, IEDM |
|---|---|
| Volume | 2021-December |
| ISSN (Print) | 0163-1918 |
Conference
| Conference | 2021 IEEE International Electron Devices Meeting, IEDM 2021 |
|---|---|
| Country/Territory | United States |
| City | San Francisco |
| Period | 11/12/21 → 16/12/21 |
Bibliographical note
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