First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering

X. R. Yu; W. H. Chang; T. C. Hong; P. J. Sung; A. Agarwal; G. L. Luo; C. T. Wu; K. H. Kao; C. J. Su; S. W. Chang; W. H. Lu; P. Y. Fu; J. H. Lin; P. H. Wu; T. C. Cho; W. C.Yu Ma; D. D. Lu; T. S. Chao; T. Maeda; Y. J. Lee; W. F. Wu; W. K. Yeh; Y. H. Wang

doi:10.1109/VLSITechnologyandCir46769.2022.9830316

First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering

X. R. Yu
, W. H. Chang
, T. C. Hong
, P. J. Sung
, A. Agarwal
, G. L. Luo
, C. T. Wu
, K. H. Kao
, C. J. Su
, S. W. Chang
, W. H. Lu
, P. Y. Fu
, J. H. Lin
, P. H. Wu
, T. C. Cho
, W. C.Yu Ma
, D. D. Lu
, T. S. Chao
, T. Maeda
, Y. J. Lee

W. F. Wu, W. K. Yeh, Y. H. Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

To solve the mobility balance issue in nanosheet FETs (NSFETs) and complementary FETs (CFETs), the aggressive approach using hetero-oriented integration with Ge channels was demonstrated by low temperature hetero-layer bonding technology (LT-HBT). Good manufacturability of the hetero-oriented Ge platform was verified with XRD 2?-? scan, Raman spectra, Selected Area Diffraction (SAD), and Converged Beam Electron Diffraction (CBED). Balanced device performance in terms of C-V, ID-VG, ID-VD and ?c for Ge (111) nFET and Ge (100) pFET was achieved, leading to better VTCs and voltage gains.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	399-400
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830316
State	Published - 2022
Externally published	Yes
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 06 2022 → 17 06 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830316

Cite this

Yu, X. R., Chang, W. H., Hong, T. C., Sung, P. J., Agarwal, A., Luo, G. L., Wu, C. T., Kao, K. H., Su, C. J., Chang, S. W., Lu, W. H., Fu, P. Y., Lin, J. H., Wu, P. H., Cho, T. C., Ma, W. C. Y., Lu, D. D., Chao, T. S., Maeda, T., ... Wang, Y. H. (2022). First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 399-400). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830316

Yu, X. R. ; Chang, W. H. ; Hong, T. C. et al. / First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering. 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 399-400 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{1042d5c53413454cb803faaf9e05d5ac,

title = "First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering",

abstract = "To solve the mobility balance issue in nanosheet FETs (NSFETs) and complementary FETs (CFETs), the aggressive approach using hetero-oriented integration with Ge channels was demonstrated by low temperature hetero-layer bonding technology (LT-HBT). Good manufacturability of the hetero-oriented Ge platform was verified with XRD 2?-? scan, Raman spectra, Selected Area Diffraction (SAD), and Converged Beam Electron Diffraction (CBED). Balanced device performance in terms of C-V, ID-VG, ID-VD and ?c for Ge (111) nFET and Ge (100) pFET was achieved, leading to better VTCs and voltage gains.",

author = "Yu, \{X. R.\} and Chang, \{W. H.\} and Hong, \{T. C.\} and Sung, \{P. J.\} and A. Agarwal and Luo, \{G. L.\} and Wu, \{C. T.\} and Kao, \{K. H.\} and Su, \{C. J.\} and Chang, \{S. W.\} and Lu, \{W. H.\} and Fu, \{P. Y.\} and Lin, \{J. H.\} and Wu, \{P. H.\} and Cho, \{T. C.\} and Ma, \{W. C.Yu\} and Lu, \{D. D.\} and Chao, \{T. S.\} and T. Maeda and Lee, \{Y. J.\} and Wu, \{W. F.\} and Yeh, \{W. K.\} and Wang, \{Y. H.\}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830316",

language = "英语",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "399--400",

booktitle = "2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022",

address = "美国",

}

Yu, XR, Chang, WH, Hong, TC, Sung, PJ, Agarwal, A, Luo, GL, Wu, CT, Kao, KH, Su, CJ, Chang, SW, Lu, WH, Fu, PY, Lin, JH, Wu, PH, Cho, TC, Ma, WCY, Lu, DD, Chao, TS, Maeda, T, Lee, YJ, Wu, WF, Yeh, WK & Wang, YH 2022, First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 399-400, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830316

First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering. / Yu, X. R.; Chang, W. H.; Hong, T. C. et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 399-400 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yu, X. R.

AU - Chang, W. H.

AU - Hong, T. C.

AU - Sung, P. J.

AU - Agarwal, A.

AU - Luo, G. L.

AU - Wu, C. T.

AU - Kao, K. H.

AU - Su, C. J.

AU - Chang, S. W.

AU - Lu, W. H.

AU - Fu, P. Y.

AU - Lin, J. H.

AU - Wu, P. H.

AU - Cho, T. C.

AU - Ma, W. C.Yu

AU - Lu, D. D.

AU - Chao, T. S.

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AU - Lee, Y. J.

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N2 - To solve the mobility balance issue in nanosheet FETs (NSFETs) and complementary FETs (CFETs), the aggressive approach using hetero-oriented integration with Ge channels was demonstrated by low temperature hetero-layer bonding technology (LT-HBT). Good manufacturability of the hetero-oriented Ge platform was verified with XRD 2?-? scan, Raman spectra, Selected Area Diffraction (SAD), and Converged Beam Electron Diffraction (CBED). Balanced device performance in terms of C-V, ID-VG, ID-VD and ?c for Ge (111) nFET and Ge (100) pFET was achieved, leading to better VTCs and voltage gains.

AB - To solve the mobility balance issue in nanosheet FETs (NSFETs) and complementary FETs (CFETs), the aggressive approach using hetero-oriented integration with Ge channels was demonstrated by low temperature hetero-layer bonding technology (LT-HBT). Good manufacturability of the hetero-oriented Ge platform was verified with XRD 2?-? scan, Raman spectra, Selected Area Diffraction (SAD), and Converged Beam Electron Diffraction (CBED). Balanced device performance in terms of C-V, ID-VG, ID-VD and ?c for Ge (111) nFET and Ge (100) pFET was achieved, leading to better VTCs and voltage gains.

UR - https://www.scopus.com/pages/publications/85135207895

U2 - 10.1109/VLSITechnologyandCir46769.2022.9830316

DO - 10.1109/VLSITechnologyandCir46769.2022.9830316

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T3 - Digest of Technical Papers - Symposium on VLSI Technology

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BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 12 June 2022 through 17 June 2022

ER -

Yu XR, Chang WH, Hong TC, Sung PJ, Agarwal A, Luo GL et al. First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 399-400. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830316

First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering

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