Abstract
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm.
Original language | English |
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Pages | 96-104 |
Number of pages | 9 |
State | Published - 1997 |
Externally published | Yes |
Event | Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 - Zurich, Switz Duration: 14 07 1997 → 16 07 1997 |
Conference
Conference | Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 |
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City | Zurich, Switz |
Period | 14/07/97 → 16/07/97 |