Flexible data-interlacing architecture for full-search block-matching algorithm

Yeong Kang Lai*, Liang Gee Chen, Yung Pin Lee

*Corresponding author for this work

Research output: Contribution to conferenceConference Paperpeer-review

1 Scopus citations

Abstract

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm.

Original languageEnglish
Pages96-104
Number of pages9
StatePublished - 1997
Externally publishedYes
EventProceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 - Zurich, Switz
Duration: 14 07 199716 07 1997

Conference

ConferenceProceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97
CityZurich, Switz
Period14/07/9716/07/97

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