FPGA-Based depth separable convolution neural network

Yeong Kang Lai; Yu Hao Hwang

doi:10.1109/ICCE46568.2020.9043044

FPGA-Based depth separable convolution neural network

Yeong Kang Lai, Yu Hao Hwang

National Chung Hsing University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In order to enable convolution neural network (CNN) to be deployed on a Field Programmable Gate Array (FPGA), this study builds a lightweight convolutional neural network that can be separated by a depth to reduce the amount of parameters and computations stored. We replaced the standard convolution operation with a separate convolution operation, and proposed a hardware accelerator architecture that can handle differently sized depth-separable convolution operations, using parallelization to efficiently utilize hardware resources for depth separable convolution. Therefore, data can be reused to reduce number of memory accesses. This hardware accelerator can achieve 588 frames per second and 37.88M ops/sec throughput at 100MHz clock.

Original language	English
Title of host publication	2020 IEEE International Conference on Consumer Electronics, ICCE 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728151861
DOIs	https://doi.org/10.1109/ICCE46568.2020.9043044
State	Published - 01 2020
Externally published	Yes
Event	2020 IEEE International Conference on Consumer Electronics, ICCE 2020 - Las Vegas, United States Duration: 04 01 2020 → 06 01 2020

Publication series

Name	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
Volume	2020-January
ISSN (Print)	0747-668X

Conference

Conference	2020 IEEE International Conference on Consumer Electronics, ICCE 2020
Country/Territory	United States
City	Las Vegas
Period	04/01/20 → 06/01/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Access to Document

10.1109/ICCE46568.2020.9043044

Cite this

Lai, Y. K., & Hwang, Y. H. (2020). FPGA-Based depth separable convolution neural network. In 2020 IEEE International Conference on Consumer Electronics, ICCE 2020 Article 9043044 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics; Vol. 2020-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE46568.2020.9043044

@inproceedings{50c767482df5423cb6ac0b7aa691a3da,

title = "FPGA-Based depth separable convolution neural network",

abstract = "In order to enable convolution neural network (CNN) to be deployed on a Field Programmable Gate Array (FPGA), this study builds a lightweight convolutional neural network that can be separated by a depth to reduce the amount of parameters and computations stored. We replaced the standard convolution operation with a separate convolution operation, and proposed a hardware accelerator architecture that can handle differently sized depth-separable convolution operations, using parallelization to efficiently utilize hardware resources for depth separable convolution. Therefore, data can be reused to reduce number of memory accesses. This hardware accelerator can achieve 588 frames per second and 37.88M ops/sec throughput at 100MHz clock.",

author = "Lai, {Yeong Kang} and Hwang, {Yu Hao}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE International Conference on Consumer Electronics, ICCE 2020 ; Conference date: 04-01-2020 Through 06-01-2020",

year = "2020",

month = jan,

doi = "10.1109/ICCE46568.2020.9043044",

language = "英语",

series = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE International Conference on Consumer Electronics, ICCE 2020",

address = "美国",

}

Lai, YK & Hwang, YH 2020, FPGA-Based depth separable convolution neural network. in 2020 IEEE International Conference on Consumer Electronics, ICCE 2020., 9043044, Digest of Technical Papers - IEEE International Conference on Consumer Electronics, vol. 2020-January, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE International Conference on Consumer Electronics, ICCE 2020, Las Vegas, United States, 04/01/20. https://doi.org/10.1109/ICCE46568.2020.9043044

FPGA-Based depth separable convolution neural network. / Lai, Yeong Kang; Hwang, Yu Hao.
2020 IEEE International Conference on Consumer Electronics, ICCE 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9043044 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics; Vol. 2020-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - FPGA-Based depth separable convolution neural network

AU - Lai, Yeong Kang

AU - Hwang, Yu Hao

PY - 2020/1

Y1 - 2020/1

N2 - In order to enable convolution neural network (CNN) to be deployed on a Field Programmable Gate Array (FPGA), this study builds a lightweight convolutional neural network that can be separated by a depth to reduce the amount of parameters and computations stored. We replaced the standard convolution operation with a separate convolution operation, and proposed a hardware accelerator architecture that can handle differently sized depth-separable convolution operations, using parallelization to efficiently utilize hardware resources for depth separable convolution. Therefore, data can be reused to reduce number of memory accesses. This hardware accelerator can achieve 588 frames per second and 37.88M ops/sec throughput at 100MHz clock.

AB - In order to enable convolution neural network (CNN) to be deployed on a Field Programmable Gate Array (FPGA), this study builds a lightweight convolutional neural network that can be separated by a depth to reduce the amount of parameters and computations stored. We replaced the standard convolution operation with a separate convolution operation, and proposed a hardware accelerator architecture that can handle differently sized depth-separable convolution operations, using parallelization to efficiently utilize hardware resources for depth separable convolution. Therefore, data can be reused to reduce number of memory accesses. This hardware accelerator can achieve 588 frames per second and 37.88M ops/sec throughput at 100MHz clock.

UR - http://www.scopus.com/inward/record.url?scp=85082629690&partnerID=8YFLogxK

U2 - 10.1109/ICCE46568.2020.9043044

DO - 10.1109/ICCE46568.2020.9043044

M3 - 会议稿件

AN - SCOPUS:85082629690

T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

BT - 2020 IEEE International Conference on Consumer Electronics, ICCE 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE International Conference on Consumer Electronics, ICCE 2020

Y2 - 4 January 2020 through 6 January 2020

ER -

FPGA-Based depth separable convolution neural network

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