FPGA demonstration for WLAN-OFDM baseband receiver

The FPGA demonstration for WLAN-OFDM baseband receiver is presented in this paper. In this OFDM baseband receiver, the CORDIC computing is employed to realize various arithmetics of baseband signal process and then to reduce the computational complexity of baseband receiver. For a large open office channel with 100 ns RMS delay spread, the measured EVMs of WLAN-OFDM baseband receiver are −13.3, −16.6, −25.4 and −31.0 dB for BPSK, QPSK, 16-QAM and 64-QAM, respectively. Finally, the physical design of WLAN-OFDM baseband receiver with 0.18 µm 1P6M CMOS technology indicates that the core area and power consumption are 1.2 mm² (1094 µm × 1092 µm) and 33.2 mW, respectively, with supply voltage of 1.8 V and operating clock of 40 MHz.