TY - GEN
T1 - FPGA prototype for WLAN OFDM baseband with STPE of I/Q mismatch self calibration algorithm
AU - Hsu, Chia Hung
AU - Wu, Chih Feng
AU - Wang, Chorng Kuang
PY - 2005
Y1 - 2005
N2 - Based on the single tone power evaluation (STPE), a self-calibration algorithm of I/Q mismatch is proposed for the IEEE 802.11a WLAN systems. The self-calibration algorithm is performed by the digital baseband at transceiver start-up to measure the signal power of the single tone signal, which is located at the double frequency band at the receiver. Furthermore, the residual I/Q mismatch is tracked during the physical data transmission. Therefore, the design requirements of the RF front-end for the WLAN OFDM transceiver are alleviated. According to the proposed algorithm, the residual signal-to-noise ratio (SNR) degradation is totally less than 0.5-dB with ±5% gain mismatch (ΔG) and ±5° phase mismatch (Δθ) in the transmitter and receiver respectively, and carrier frequency offset (CFO = ± 232kHz). Finally, the prototype of the IEEE 802.11a WLAN baseband is realized by the Altera Stratix EP1S80 DSP development board with about 32000 logic elements at 40MHz.
AB - Based on the single tone power evaluation (STPE), a self-calibration algorithm of I/Q mismatch is proposed for the IEEE 802.11a WLAN systems. The self-calibration algorithm is performed by the digital baseband at transceiver start-up to measure the signal power of the single tone signal, which is located at the double frequency band at the receiver. Furthermore, the residual I/Q mismatch is tracked during the physical data transmission. Therefore, the design requirements of the RF front-end for the WLAN OFDM transceiver are alleviated. According to the proposed algorithm, the residual signal-to-noise ratio (SNR) degradation is totally less than 0.5-dB with ±5% gain mismatch (ΔG) and ±5° phase mismatch (Δθ) in the transmitter and receiver respectively, and carrier frequency offset (CFO = ± 232kHz). Finally, the prototype of the IEEE 802.11a WLAN baseband is realized by the Altera Stratix EP1S80 DSP development board with about 32000 logic elements at 40MHz.
UR - https://www.scopus.com/pages/publications/34250729050
U2 - 10.1109/ASSCC.2005.251789
DO - 10.1109/ASSCC.2005.251789
M3 - 会议稿件
AN - SCOPUS:34250729050
SN - 0780391624
SN - 9780780391628
T3 - 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
SP - 509
EP - 512
BT - 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PB - IEEE Computer Society
T2 - 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Y2 - 1 November 2005 through 3 November 2005
ER -