Fully automated layout generators for high-performance analog VLSI modules

Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.