Fully automated layout generators for high-performance analog VLSI modules

Ji Chien Lee; Sudhir M. Gowda; Bing J. Sheu

Fully automated layout generators for high-performance analog VLSI modules

Ji Chien Lee^*
, Sudhir M. Gowda
, Bing J. Sheu

^*Corresponding author for this work

University of Southern California

Research output: Contribution to conference › Conference Paper › peer-review

4 Scopus citations

Abstract

Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.

Original language	English
Pages	893-896
Number of pages	4
State	Published - 1989
Externally published	Yes
Event	4th IEEE Region 10th International Conference - TENCON '89 - Bombay, India Duration: 22 11 1989 → 24 11 1989

Conference

Conference	4th IEEE Region 10th International Conference - TENCON '89
City	Bombay, India
Period	22/11/89 → 24/11/89

Cite this

@conference{3214ca6f9a274a9db10e31c945a20875,

title = "Fully automated layout generators for high-performance analog VLSI modules",

abstract = "Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.",

author = "Lee, \{Ji Chien\} and Gowda, \{Sudhir M.\} and Sheu, \{Bing J.\}",

year = "1989",

language = "英语",

pages = "893--896",

note = "4th IEEE Region 10th International Conference - TENCON '89 ; Conference date: 22-11-1989 Through 24-11-1989",

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TY - CONF

T1 - Fully automated layout generators for high-performance analog VLSI modules

AU - Lee, Ji Chien

AU - Gowda, Sudhir M.

AU - Sheu, Bing J.

PY - 1989

Y1 - 1989

N2 - Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.

AB - Algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.

UR - https://www.scopus.com/pages/publications/0024774424

M3 - 论文

AN - SCOPUS:0024774424

SP - 893

EP - 896

T2 - 4th IEEE Region 10th International Conference - TENCON '89

Y2 - 22 November 1989 through 24 November 1989

ER -

Fully automated layout generators for high-performance analog VLSI modules

Abstract

Conference

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