Gate-induced drain leakage (GIDL) improvement for millisecond flash anneal (MFLA) in DRAM application

In this paper, we successfully demonstrated gate-induced drain leakage (GIDL) improvements by millisecond Flash anneal (MFLA) on a DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application. The periphery NMOS off current was reduced by 36%. This off-current improvement reduced the standby current by 5% in a DRAM functional test. The GIDL reductions for an NMOS array and periphery N- and PMOSs were 14.5%, 15%, and 39%, respectively. A model for GIDL improvement by MFLA application to DRAM production was proposed. It is believed that the main GIDL-impacted factor was the high electric field caused by defect-assisted tunneling and junction profile abruptness under the gate edge. Bright field and weak-beam dark-field TEM images showed perfect dislocation loops and fault dislocation loops staying in the {113} plane with a size of around 17 × 20 nm in the junction area. These defects could be one of the leakage sources for a defect-assisted trap charge, leading to trap-assisted tunneling.