General-Purpose Neural Chips with Electrically Programmable Synapses and Gain-Adjustable Neurons

Bang W. Lee; Bing J. Sheu

doi:10.1109/4.149421

General-Purpose Neural Chips with Electrically Programmable Synapses and Gain-Adjustable Neurons

Bang W. Lee, Bing J. Sheu

University of Southern California

Research output: Contribution to journal › Journal Article › peer-review

13 Scopus citations

Abstract

Circuit cells for DRAM-style programmable syn- apses and gain-adjustable neurons, which achieve high packing density and hardware annealing, are described. The 8-b accuracy in synapse weights can be achieved in a 0.2-s refresh cycle and the gain-adjustable neurons can be used to apply the hardware annealing technique for efficient searching of the optimal solution.

Original language	English
Pages (from-to)	1299-1302
Number of pages	4
Journal	IEEE Journal of Solid-State Circuits
Volume	27
Issue number	9
DOIs	https://doi.org/10.1109/4.149421
State	Published - 09 1992
Externally published	Yes

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title = "General-Purpose Neural Chips with Electrically Programmable Synapses and Gain-Adjustable Neurons",

abstract = "Circuit cells for DRAM-style programmable syn- apses and gain-adjustable neurons, which achieve high packing density and hardware annealing, are described. The 8-b accuracy in synapse weights can be achieved in a 0.2-s refresh cycle and the gain-adjustable neurons can be used to apply the hardware annealing technique for efficient searching of the optimal solution.",

author = "Lee, \{Bang W.\} and Sheu, \{Bing J.\}",

year = "1992",

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AU - Lee, Bang W.

AU - Sheu, Bing J.

PY - 1992/9

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N2 - Circuit cells for DRAM-style programmable syn- apses and gain-adjustable neurons, which achieve high packing density and hardware annealing, are described. The 8-b accuracy in synapse weights can be achieved in a 0.2-s refresh cycle and the gain-adjustable neurons can be used to apply the hardware annealing technique for efficient searching of the optimal solution.

AB - Circuit cells for DRAM-style programmable syn- apses and gain-adjustable neurons, which achieve high packing density and hardware annealing, are described. The 8-b accuracy in synapse weights can be achieved in a 0.2-s refresh cycle and the gain-adjustable neurons can be used to apply the hardware annealing technique for efficient searching of the optimal solution.

UR - https://www.scopus.com/pages/publications/0026925756

U2 - 10.1109/4.149421

DO - 10.1109/4.149421

M3 - 文章

AN - SCOPUS:0026925756

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 9

ER -

General-Purpose Neural Chips with Electrically Programmable Synapses and Gain-Adjustable Neurons

Abstract

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