TY - JOUR
T1 - Generalised approach to automatic custom layout of analogue ICs
AU - Chen, D. J.
AU - Sheu, B. J.
PY - 1992
Y1 - 1992
N2 - An automatic custom analogue IC layout methodology is presented which employs primitive cell recognition, critical net analysis, and self-constructive floorplanning and routing techniques. Based on this methodology, a general-purpose analogue circuit module layout generator, SLAM, has been developed. Given the schematic netlist of an arbitrary analogue MOS circuits module, SLAM can quickly generate a high-quality custom layout to some desired aspect ratio. With a simple extension of the hierarchy, this method can also handle more complex analogue subsystems. Special layout constraints are automatically analysed for each analogue circuit and properly incorporated into the layout generation on each level of the circuit hierarchy to achieve both high performance and overall area efficiency. Experimental results on common analogue VLSI building blocks such as operational amplifier, comparator and neural circuit modules are presented.
AB - An automatic custom analogue IC layout methodology is presented which employs primitive cell recognition, critical net analysis, and self-constructive floorplanning and routing techniques. Based on this methodology, a general-purpose analogue circuit module layout generator, SLAM, has been developed. Given the schematic netlist of an arbitrary analogue MOS circuits module, SLAM can quickly generate a high-quality custom layout to some desired aspect ratio. With a simple extension of the hierarchy, this method can also handle more complex analogue subsystems. Special layout constraints are automatically analysed for each analogue circuit and properly incorporated into the layout generation on each level of the circuit hierarchy to achieve both high performance and overall area efficiency. Experimental results on common analogue VLSI building blocks such as operational amplifier, comparator and neural circuit modules are presented.
UR - http://www.scopus.com/inward/record.url?scp=0026907627&partnerID=8YFLogxK
U2 - 10.1049/ip-g-2.1992.0076
DO - 10.1049/ip-g-2.1992.0076
M3 - 文章
AN - SCOPUS:0026907627
SN - 0956-3768
VL - 139
SP - 481
EP - 490
JO - IEE Proceedings, Part G: Circuits, Devices and Systems
JF - IEE Proceedings, Part G: Circuits, Devices and Systems
IS - 4
ER -