GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing

Chin Fu Nien; Yi Jou Hsiao; Hsiang Yun Cheng; Cheng Yu Wen; Ya Cheng Ko; Che Ching Lin

doi:10.23919/DATE48585.2020.9116232

GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing

Chin Fu Nien, Yi Jou Hsiao, Hsiang Yun Cheng, Cheng Yu Wen, Ya Cheng Ko, Che Ching Lin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

Graph processing has attracted a lot of interests in recent years as it plays a key role to analyze huge datasets. ReRAM-based accelerators provide a promising solution to accelerate graph processing. However, the intrinsic stochastic behavior of ReRAM devices makes its computation results unreliable. In this paper, we build a simulation platform to analyze the impact of non-ideal ReRAM devices on the error rates of various graph algorithms. We show that the characteristic of the targeted graph algorithm and the type of ReRAM computations employed greatly affect the error rates. Using representative graph algorithms as case studies, we demonstrate that our simulation platform can guide chip designers to select better design options and develop new techniques to improve reliability.

Original language	English
Title of host publication	Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
Editors	Giorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1478-1483
Number of pages	6
ISBN (Electronic)	9783981926347
DOIs	https://doi.org/10.23919/DATE48585.2020.9116232
State	Published - 03 2020
Externally published	Yes
Event	2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France Duration: 09 03 2020 → 13 03 2020

Publication series

Name	Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

Conference

Conference	2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
Country/Territory	France
City	Grenoble
Period	09/03/20 → 13/03/20

Bibliographical note

Publisher Copyright:
© 2020 EDAA.

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10.23919/DATE48585.2020.9116232

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Nien, C. F., Hsiao, Y. J., Cheng, H. Y., Wen, C. Y., Ko, Y. C., & Lin, C. C. (2020). GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. In G. Di Natale, C. Bolchini, & E.-I. Vatajelu (Eds.), Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 (pp. 1478-1483). Article 9116232 (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE48585.2020.9116232

Nien, Chin Fu ; Hsiao, Yi Jou ; Cheng, Hsiang Yun et al. / GraphRSim : A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. editor / Giorgio Di Natale ; Cristiana Bolchini ; Elena-Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 1478-1483 (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

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abstract = "Graph processing has attracted a lot of interests in recent years as it plays a key role to analyze huge datasets. ReRAM-based accelerators provide a promising solution to accelerate graph processing. However, the intrinsic stochastic behavior of ReRAM devices makes its computation results unreliable. In this paper, we build a simulation platform to analyze the impact of non-ideal ReRAM devices on the error rates of various graph algorithms. We show that the characteristic of the targeted graph algorithm and the type of ReRAM computations employed greatly affect the error rates. Using representative graph algorithms as case studies, we demonstrate that our simulation platform can guide chip designers to select better design options and develop new techniques to improve reliability.",

author = "Nien, {Chin Fu} and Hsiao, {Yi Jou} and Cheng, {Hsiang Yun} and Wen, {Cheng Yu} and Ko, {Ya Cheng} and Lin, {Che Ching}",

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year = "2020",

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doi = "10.23919/DATE48585.2020.9116232",

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Nien, CF, Hsiao, YJ, Cheng, HY, Wen, CY, Ko, YC & Lin, CC 2020, GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. in G Di Natale, C Bolchini & E-I Vatajelu (eds), Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020., 9116232, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, Institute of Electrical and Electronics Engineers Inc., pp. 1478-1483, 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, Grenoble, France, 09/03/20. https://doi.org/10.23919/DATE48585.2020.9116232

GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. / Nien, Chin Fu; Hsiao, Yi Jou; Cheng, Hsiang Yun et al.
Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. ed. / Giorgio Di Natale; Cristiana Bolchini; Elena-Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2020. p. 1478-1483 9116232 (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Nien, Chin Fu

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AU - Wen, Cheng Yu

AU - Ko, Ya Cheng

AU - Lin, Che Ching

PY - 2020/3

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AB - Graph processing has attracted a lot of interests in recent years as it plays a key role to analyze huge datasets. ReRAM-based accelerators provide a promising solution to accelerate graph processing. However, the intrinsic stochastic behavior of ReRAM devices makes its computation results unreliable. In this paper, we build a simulation platform to analyze the impact of non-ideal ReRAM devices on the error rates of various graph algorithms. We show that the characteristic of the targeted graph algorithm and the type of ReRAM computations employed greatly affect the error rates. Using representative graph algorithms as case studies, we demonstrate that our simulation platform can guide chip designers to select better design options and develop new techniques to improve reliability.

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Nien CF, Hsiao YJ, Cheng HY, Wen CY, Ko YC, Lin CC. GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. In Di Natale G, Bolchini C, Vatajelu EI, editors, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 1478-1483. 9116232. (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020). doi: 10.23919/DATE48585.2020.9116232

GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing

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