Hardware accelerator for boosting convolution computation in image classification applications

Meng Chou Chang; Ze Gang Pan; Jyun Liang Chen

doi:10.1109/GCCE.2017.8229395

Hardware accelerator for boosting convolution computation in image classification applications

Meng Chou Chang
, Ze Gang Pan
, Jyun Liang Chen

National Changhua University of Education

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

Original language	English
Title of host publication	2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509040452
DOIs	https://doi.org/10.1109/GCCE.2017.8229395
State	Published - 19 12 2017
Externally published	Yes
Event	6th IEEE Global Conference on Consumer Electronics, GCCE 2017 - Nagoya, Japan Duration: 24 10 2017 → 27 10 2017

Publication series

Name	2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017
Volume	2017-January

Conference

Conference	6th IEEE Global Conference on Consumer Electronics, GCCE 2017
Country/Territory	Japan
City	Nagoya
Period	24/10/17 → 27/10/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Keywords

Convolutional neural network
image classification

Access to Document

10.1109/GCCE.2017.8229395

Cite this

Chang, M. C., Pan, Z. G., & Chen, J. L. (2017). Hardware accelerator for boosting convolution computation in image classification applications. In 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017 (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; Vol. 2017-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/GCCE.2017.8229395

@inproceedings{70bf7e3662864642a38f71e9095b4bda,

title = "Hardware accelerator for boosting convolution computation in image classification applications",

abstract = "In a convolutional neural network (CNN), convolution calculation can account for about 90\% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).",

keywords = "Convolutional neural network, image classification",

author = "Chang, \{Meng Chou\} and Pan, \{Ze Gang\} and Chen, \{Jyun Liang\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 6th IEEE Global Conference on Consumer Electronics, GCCE 2017 ; Conference date: 24-10-2017 Through 27-10-2017",

year = "2017",

month = dec,

day = "19",

doi = "10.1109/GCCE.2017.8229395",

language = "英语",

series = "2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017",

address = "美国",

}

Chang, MC, Pan, ZG & Chen, JL 2017, Hardware accelerator for boosting convolution computation in image classification applications. in 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017, vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., 6th IEEE Global Conference on Consumer Electronics, GCCE 2017, Nagoya, Japan, 24/10/17. https://doi.org/10.1109/GCCE.2017.8229395

Hardware accelerator for boosting convolution computation in image classification applications. / Chang, Meng Chou; Pan, Ze Gang; Chen, Jyun Liang.
2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017; Vol. 2017-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Hardware accelerator for boosting convolution computation in image classification applications

AU - Chang, Meng Chou

AU - Pan, Ze Gang

AU - Chen, Jyun Liang

PY - 2017/12/19

Y1 - 2017/12/19

N2 - In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

AB - In a convolutional neural network (CNN), convolution calculation can account for about 90% of the total processing work. This paper presents the design of a convolution hardware accelerator (CHA) which can support efficient matrix multiplication to speed up the convolution calculation. In our experiment, when a RISC-V Rocket processor is used to simulate the operation of a CNN for image classification, it can achieve a performance speedup of 30.82 with the help of the convolution hardware accelerator (CHA).

KW - Convolutional neural network

KW - image classification

UR - https://www.scopus.com/pages/publications/85045731495

U2 - 10.1109/GCCE.2017.8229395

DO - 10.1109/GCCE.2017.8229395

M3 - 会议稿件

AN - SCOPUS:85045731495

T3 - 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017

BT - 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th IEEE Global Conference on Consumer Electronics, GCCE 2017

Y2 - 24 October 2017 through 27 October 2017

ER -

Hardware accelerator for boosting convolution computation in image classification applications

Abstract

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Keywords

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