Hardware annealing for fast retrieval of optimal solutions in Hopfield neural networks

Bing J. Sheu*, Bang W. Lee, Chia Fen Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Due to the feedback characteristics of Hopfield networks, the solutions often get stuck at local minima where the objective functions have surrounding barriers. The theory and procedure of hardware annealing, which can retrieve the optimal solution in parallel, have been developed. In hardware annealing, voltage gains of output neurons in asynchronous VLSI neural chips are increased from an initial low value to a final high value in a continuous fashion. Hardware annealing can be applied to pure analog and mixed analog-digital neurocomputing systems. It achieves a speed-up factor of more than 10,000 times over simulated annealing on a SUN-3/60 workstation.

Original languageEnglish
Title of host publicationProceedings. IJCNN - International Joint Conference on Neural Networks
Editors Anon
PublisherPubl by IEEE
Pages327-332
Number of pages6
ISBN (Print)0780301641
StatePublished - 1992
Externally publishedYes
EventInternational Joint Conference on Neural Networks - IJCNN-91-Seattle - Seattle, WA, USA
Duration: 08 07 199112 07 1991

Publication series

NameProceedings. IJCNN - International Joint Conference on Neural Networks

Conference

ConferenceInternational Joint Conference on Neural Networks - IJCNN-91-Seattle
CitySeattle, WA, USA
Period08/07/9112/07/91

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