Hardware annealing in electronic neural networks

Bang W. Lee; Bing J. Sheu

doi:10.1109/31.101312

Hardware annealing in electronic neural networks

Bang W. Lee^*
, Bing J. Sheu

^*Corresponding author for this work

University of Southern California

Research output: Contribution to journal › Journal Article › peer-review

22 Scopus citations

Abstract

A simulated hardware annealing process for electronic neural circuits is derived from the analogy between the temperature in a Boltzmann machine and the amplifier gain in a VLSI chip. Here, varying the amplifier gain is equivalent to changing the temperature of the probability function in a Boltzman machine. Decrease in the amplifier voltage gain is equivalent to temperature increase. The beginning and final annealing temperatures for the hardware annealing can be precisely determined. Theory and experimental results on a 4-b Hopfield analog-to-digital converters with simulated annealing are presented.

Original language	English
Pages (from-to)	134-137
Number of pages	4
Journal	IEEE Transactions on Circuits and Systems
Volume	38
Issue number	1
DOIs	https://doi.org/10.1109/31.101312
State	Published - 1991
Externally published	Yes

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@article{d85a4632e3604784963bfeb6b95832aa,

title = "Hardware annealing in electronic neural networks",

abstract = "A simulated hardware annealing process for electronic neural circuits is derived from the analogy between the temperature in a Boltzmann machine and the amplifier gain in a VLSI chip. Here, varying the amplifier gain is equivalent to changing the temperature of the probability function in a Boltzman machine. Decrease in the amplifier voltage gain is equivalent to temperature increase. The beginning and final annealing temperatures for the hardware annealing can be precisely determined. Theory and experimental results on a 4-b Hopfield analog-to-digital converters with simulated annealing are presented.",

author = "Lee, \{Bang W.\} and Sheu, \{Bing J.\}",

year = "1991",

doi = "10.1109/31.101312",

language = "英语",

volume = "38",

pages = "134--137",

journal = "IEEE Transactions on Circuits and Systems",

issn = "0098-4094",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Hardware annealing in electronic neural networks

AU - Lee, Bang W.

AU - Sheu, Bing J.

PY - 1991

Y1 - 1991

N2 - A simulated hardware annealing process for electronic neural circuits is derived from the analogy between the temperature in a Boltzmann machine and the amplifier gain in a VLSI chip. Here, varying the amplifier gain is equivalent to changing the temperature of the probability function in a Boltzman machine. Decrease in the amplifier voltage gain is equivalent to temperature increase. The beginning and final annealing temperatures for the hardware annealing can be precisely determined. Theory and experimental results on a 4-b Hopfield analog-to-digital converters with simulated annealing are presented.

AB - A simulated hardware annealing process for electronic neural circuits is derived from the analogy between the temperature in a Boltzmann machine and the amplifier gain in a VLSI chip. Here, varying the amplifier gain is equivalent to changing the temperature of the probability function in a Boltzman machine. Decrease in the amplifier voltage gain is equivalent to temperature increase. The beginning and final annealing temperatures for the hardware annealing can be precisely determined. Theory and experimental results on a 4-b Hopfield analog-to-digital converters with simulated annealing are presented.

UR - https://www.scopus.com/pages/publications/0025746730

U2 - 10.1109/31.101312

DO - 10.1109/31.101312

M3 - 文章

AN - SCOPUS:0025746730

SN - 0098-4094

VL - 38

SP - 134

EP - 137

JO - IEEE Transactions on Circuits and Systems

JF - IEEE Transactions on Circuits and Systems

IS - 1

ER -

Hardware annealing in electronic neural networks

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