Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation

Lien Fei Chen; Shien Yu Huang; Chi Yao Liao; Yeong Kang Lai

doi:10.1109/ISCAS.2009.5118091

Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation

Lien Fei Chen^*
, Shien Yu Huang
, Chi Yao Liao
, Yeong Kang Lai

^*Corresponding author for this work

National Chung Hsing University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At the first step, the candidate block down-sampling technique and the multi-level successive elimination algorithm (MSEA) with fixed 16x16 block-matching are adopted to rapidly find the possible regions. Then, the local full search method with VBSME is utilized at these possible regions to parallel calculate the minimum SAD of the 41MVs. According to the analysis, proposed fast algorithm not only has 5% computational complexity compared with the full search block-matching algorithm (FSBMA), but also preserves fine RD performance. In the light of our hardware evaluation, the proposed fast algorithm can easily achieve the real-time HDTV video coding requirement with the 64 processing elements (PEs) architecture.

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages	1657-1660
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5118091
State	Published - 2009
Externally published	Yes
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan Duration: 24 05 2009 → 27 05 2009

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan
City	Taipei
Period	24/05/09 → 27/05/09

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10.1109/ISCAS.2009.5118091

Cite this

Chen, L. F., Huang, S. Y., Liao, C. Y., & Lai, Y. K. (2009). Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (pp. 1657-1660). Article 5118091 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2009.5118091

@inproceedings{e556628b8f0945058d8e5eda3c19e574,

title = "Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation",

abstract = "In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At the first step, the candidate block down-sampling technique and the multi-level successive elimination algorithm (MSEA) with fixed 16x16 block-matching are adopted to rapidly find the possible regions. Then, the local full search method with VBSME is utilized at these possible regions to parallel calculate the minimum SAD of the 41MVs. According to the analysis, proposed fast algorithm not only has 5\% computational complexity compared with the full search block-matching algorithm (FSBMA), but also preserves fine RD performance. In the light of our hardware evaluation, the proposed fast algorithm can easily achieve the real-time HDTV video coding requirement with the 64 processing elements (PEs) architecture.",

author = "Chen, \{Lien Fei\} and Huang, \{Shien Yu\} and Liao, \{Chi Yao\} and Lai, \{Yeong Kang\}",

year = "2009",

doi = "10.1109/ISCAS.2009.5118091",

language = "英语",

isbn = "9781424438280",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1657--1660",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

}

Chen, LF, Huang, SY, Liao, CY & Lai, YK 2009, Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5118091, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1657-1660, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, 24/05/09. https://doi.org/10.1109/ISCAS.2009.5118091

Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation. / Chen, Lien Fei; Huang, Shien Yu; Liao, Chi Yao et al.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 1657-1660 5118091 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Chen, Lien Fei

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AU - Liao, Chi Yao

AU - Lai, Yeong Kang

PY - 2009

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N2 - In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At the first step, the candidate block down-sampling technique and the multi-level successive elimination algorithm (MSEA) with fixed 16x16 block-matching are adopted to rapidly find the possible regions. Then, the local full search method with VBSME is utilized at these possible regions to parallel calculate the minimum SAD of the 41MVs. According to the analysis, proposed fast algorithm not only has 5% computational complexity compared with the full search block-matching algorithm (FSBMA), but also preserves fine RD performance. In the light of our hardware evaluation, the proposed fast algorithm can easily achieve the real-time HDTV video coding requirement with the 64 processing elements (PEs) architecture.

AB - In this paper, a hardware efficient coarse-to-fine fast algorithm for H.264 motion estimation is proposed. We present hardware friendly two-step searching flow to obtain the 41 MVs of the variable block size motion estimation (VBSME) efficiently. At the first step, the candidate block down-sampling technique and the multi-level successive elimination algorithm (MSEA) with fixed 16x16 block-matching are adopted to rapidly find the possible regions. Then, the local full search method with VBSME is utilized at these possible regions to parallel calculate the minimum SAD of the 41MVs. According to the analysis, proposed fast algorithm not only has 5% computational complexity compared with the full search block-matching algorithm (FSBMA), but also preserves fine RD performance. In the light of our hardware evaluation, the proposed fast algorithm can easily achieve the real-time HDTV video coding requirement with the 64 processing elements (PEs) architecture.

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Hardware efficient coarse-to-fine fast algorithm for H.264/AVC variable block size motion estimation

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